公开(公告)号：US09812414B1

公开(公告)日：2017-11-07

申请号：US15186100

申请日：2016-06-17

申请人： NANYA TECHNOLOGY CORPORATION

发明人： Po Chun Lin

IPC分类号： H01L23/48 ,  H01L23/00 ,  H01L23/538

CPC分类号： H01L24/02 ,  H01L23/5389 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/02125 ,  H01L2224/02145 ,  H01L2224/0215 ,  H01L2224/02165 ,  H01L2224/02185 ,  H01L2224/0219 ,  H01L2224/02315 ,  H01L2224/02331 ,  H01L2224/03462 ,  H01L2224/0391 ,  H01L2224/05096 ,  H01L2224/05548 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1134 ,  H01L2224/11462 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16237 ,  H01L2924/3512 ,  H01L2924/35121 ,  H01L2924/06 ,  H01L2924/00014 ,  H01L2924/014

摘要： A chip package includes a first substrate; a first insulation layer disposed over the first substrate; a conductive structure disposed within the first insulation layer; a buffering member embedded into the first insulation layer; a redistribution layer (RDL) electrically connected with the conductive structure and disposed over the conductive structure and the buffering member; and a second insulation layer disposed over the RDL, wherein a portion of the RDL is exposed from the second insulation layer and disposed over the buffering member.

公开(公告)号：US20170012005A1

公开(公告)日：2017-01-12

申请号：US15273747

申请日：2016-09-23

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Hsien-Wei CHEN ,  Chung-Ying YANG

IPC分类号： H01L23/58 ,  H01L23/00

CPC分类号： H01L23/585 ,  H01L23/3171 ,  H01L23/5283 ,  H01L23/562 ,  H01L23/564 ,  H01L2224/02165 ,  H01L2224/02166 ,  H01L2924/0002 ,  H01L2924/00

摘要： A customized seal ring for a semiconductor device is formed of multiple seal ring cells that are selected and arranged to produce a seal ring design. The cells include first cells that are coupled to ground and second cells that are not coupled to ground. The second cells that are not coupled to ground, include a higher density of metal features in an inner portion thereof, than the first seal ring cells. Dummy metal vias and other metal features that may be present in the inner portion of the second seal ring cells are absent from the inner portion of the first seal ring cells that are coupled to ground. The seal ring design may include various arrangements, including alternating and repeating sequences of the different seal ring cells.

摘要翻译： 用于半导体器件的定制密封环由多个密封环电池形成，所述多个密封环电池被选择和布置以产生密封环设计。 这些电池包括耦合到地的第一个电池和不耦合到地的第二个电池。 与第一密封环电池相比，没有耦合到地面的第二电池在其内部包括更高密度的金属特征。 可能存在于第二密封环单元的内部的虚拟金属通孔和其它金属特征不存在于耦合到地的第一密封环单元的内部。 密封环设计可以包括各种布置，包括不同密封环单元的交替和重复序列。

公开(公告)号：US09515036B2

公开(公告)日：2016-12-06

申请号：US13452507

申请日：2012-04-20

申请人： Chen-Hua Yu ,  Hao-Yi Tsai ,  Chien-Hsiun Lee ,  Chung-Shi Liu ,  Hsien-Wei Chen

发明人： Chen-Hua Yu ,  Hao-Yi Tsai ,  Chien-Hsiun Lee ,  Chung-Shi Liu ,  Hsien-Wei Chen

IPC分类号： H01L23/00

CPC分类号： H01L24/11 ,  H01L24/02 ,  H01L24/05 ,  H01L24/13 ,  H01L24/14 ,  H01L2224/02125 ,  H01L2224/02165 ,  H01L2224/02335 ,  H01L2224/0239 ,  H01L2224/024 ,  H01L2224/03464 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05024 ,  H01L2224/05027 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05562 ,  H01L2224/05567 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/05669 ,  H01L2224/1132 ,  H01L2224/1134 ,  H01L2224/11849 ,  H01L2224/13022 ,  H01L2224/13026 ,  H01L2224/13076 ,  H01L2224/13078 ,  H01L2224/13082 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/1403 ,  H01L2224/14051 ,  H01L2224/14131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/06 ,  H01L2924/351 ,  H01L2924/3512 ,  H01L2224/05552 ,  H01L2924/00

摘要： Methods and apparatus for solder connections. An apparatus includes a substrate having a conductive terminal on a surface; a passivation layer overlying the surface of the substrate and the conductive terminal; an opening in the passivation layer exposing a portion of the conductive terminal; at least one stud bump bonded to the conductive terminal in the opening and extending in a direction normal to the surface of the substrate; and a solder connection formed on the conductive terminal in the opening and enclosing the at least one stud bump. Methods for forming the solder connections are disclosed.

摘要翻译： 焊接方法和装置。 一种装置包括：在表面上具有导电端子的基板; 覆盖在衬底表面上的钝化层和导电端子; 所述钝化层中的开口暴露所述导电端子的一部分; 至少一个凸起凸块，其结合到所述开口中的所述导电端子并且沿垂直于所述基板的表面的方向延伸; 以及形成在所述开口中的所述导电端子上并且包围所述至少一个螺柱凸块的焊接连接。 公开了形成焊料连接的方法。

公开(公告)号：US09398689B2

公开(公告)日：2016-07-19

申请号：US14463049

申请日：2014-08-19

申请人： Siliconware Precision Industries Co., Ltd.

发明人： Cheng-An Chang ,  Sung-Huan Sun ,  Wen-Kai Liao ,  Chien-Hung Wu ,  Yi-Cheih Chen

IPC分类号： H05K1/03 ,  H01L23/00 ,  H01L23/498 ,  H05K3/34 ,  H01L23/31

CPC分类号： H05K1/032 ,  H01L23/3192 ,  H01L23/49816 ,  H01L23/562 ,  H01L23/564 ,  H01L24/02 ,  H01L24/05 ,  H01L24/13 ,  H01L24/94 ,  H01L2224/02165 ,  H01L2224/02235 ,  H01L2224/02331 ,  H01L2224/0401 ,  H01L2224/05571 ,  H01L2224/10145 ,  H01L2224/13021 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/94 ,  H01L2924/351 ,  H01L2924/3512 ,  H01L2924/384 ,  H05K3/3452 ,  H05K3/3457 ,  H05K2201/09909 ,  H05K2203/041 ,  H01L2224/11 ,  H01L2924/014

摘要： A substrate structure is provided, which includes: a substrate body having a plurality of conductive pads; an insulating layer formed on the substrate body and having a plurality of openings for correspondingly exposing the conductive pads; and a plurality of ring bodies formed in the openings and corresponding in position to edges of the conductive pads. As such, a plurality of conductive elements can be subsequently formed inside the ring bodies so as to be prevented by the ring bodies from expanding outward during a reflow process, thereby protecting the insulating layer from being compressed by the conductive elements and preventing cracking of the insulating layer.

摘要翻译： 提供了一种衬底结构，其包括：具有多个导电焊盘的衬底本体; 绝缘层，其形成在所述基板主体上并且具有用于相应地暴露所述导电焊盘的多个开口; 以及形成在所述开口中并且对应于所述导电垫的边缘的位置的多个环体。 因此，可以随后在环体内部形成多个导电元件，以便在回流过程中由环体向外扩张，从而保护绝缘层免受导电元件的压缩，并防止 绝缘层。

公开(公告)号：US20150214168A1

公开(公告)日：2015-07-30

申请号：US14463049

申请日：2014-08-19

申请人： Siliconware Precision Industries Co., Ltd.

发明人： Cheng-An Chang ,  Sung-Huan Sun ,  Wen-Kai Liao ,  Chien-Hung Wu ,  Yi-Cheih Chen

IPC分类号： H01L23/00 ,  H05K1/03 ,  H05K1/11

CPC分类号： H05K1/032 ,  H01L23/3192 ,  H01L23/49816 ,  H01L23/562 ,  H01L23/564 ,  H01L24/02 ,  H01L24/05 ,  H01L24/13 ,  H01L24/94 ,  H01L2224/02165 ,  H01L2224/02235 ,  H01L2224/02331 ,  H01L2224/0401 ,  H01L2224/05571 ,  H01L2224/10145 ,  H01L2224/13021 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/94 ,  H01L2924/351 ,  H01L2924/3512 ,  H01L2924/384 ,  H05K3/3452 ,  H05K3/3457 ,  H05K2201/09909 ,  H05K2203/041 ,  H01L2224/11 ,  H01L2924/014

摘要： A substrate structure is provided, which includes: a substrate body having a plurality of conductive pads; an insulating layer formed on the substrate body and having a plurality of openings for correspondingly exposing the conductive pads; and a plurality of ring bodies formed in the openings and corresponding in position to edges of the conductive pads. As such, a plurality of conductive elements can be subsequently formed inside the ring bodies so as to be prevented by the ring bodies from expanding outward during a reflow process, thereby protecting the insulating layer from being compressed by the conductive elements and preventing cracking of the insulating layer.

摘要翻译： 提供了一种衬底结构，其包括：具有多个导电焊盘的衬底本体; 绝缘层，其形成在所述基板主体上并且具有用于相应地暴露所述导电焊盘的多个开口; 以及形成在所述开口中并且对应于所述导电垫的边缘的位置的多个环体。 因此，可以随后在环体内部形成多个导电元件，以便在回流过程中由环体向外扩张，从而保护绝缘层免受导电元件的压缩，并防止 绝缘层。

公开(公告)号：US07205660B2

公开(公告)日：2007-04-17

申请号：US11186763

申请日：2005-07-22

申请人： Myeong-Soon Park ,  Hyun-Soo Chung ,  In-Young Lee ,  Jae-Sik Chung ,  Sung-Min Sim ,  Dong-Hyeon Jang ,  Young-Hee Song ,  Seung-Kwan Ryu

发明人： Myeong-Soon Park ,  Hyun-Soo Chung ,  In-Young Lee ,  Jae-Sik Chung ,  Sung-Min Sim ,  Dong-Hyeon Jang ,  Young-Hee Song ,  Seung-Kwan Ryu

IPC分类号： H01L23/48

CPC分类号： H01L23/3114 ,  H01L23/525 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/02165 ,  H01L2224/02335 ,  H01L2224/02351 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05548 ,  H01L2224/05557 ,  H01L2224/05569 ,  H01L2224/10125 ,  H01L2224/13006 ,  H01L2224/13011 ,  H01L2224/13018 ,  H01L2224/13099 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/30105 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2224/05599

摘要： A wafer level chip scale package may have a gap provided between a solder bump and a bump land. The gap may be filled with a gas. A method of manufacturing a wafer level chip scale package may involve forming a redistribution line having a first opening, forming a seed metal layer having a second opening including an undercut portion, and forming the gap using the first and the second openings.

公开(公告)号：US20230420388A1

公开(公告)日：2023-12-28

申请号：US17809386

申请日：2022-06-28

申请人： SANDISK TECHNOLOGIES LLC

发明人： Yushi YOKOMIZO

IPC分类号： H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H01L27/11556 ,  H01L27/11582

CPC分类号： H01L23/562 ,  H01L25/0657 ,  H01L25/18 ,  H01L24/08 ,  H01L27/11556 ,  H01L27/11582 ,  H01L2224/02165 ,  H01L2224/08145 ,  H01L2924/1431 ,  H01L2924/14511 ,  H01L2924/3511

摘要： A semiconductor structure includes a semiconductor device substrate, and an auxetic microstructure containing an auxetic matrix having a negative Poission's ratio.

公开(公告)号：US20230352430A1

公开(公告)日：2023-11-02

申请号：US18163576

申请日：2023-02-02

申请人： RENESAS ELECTRONICS CORPORATION

发明人： Takashi MORIYAMA

IPC分类号： H01L23/00

CPC分类号： H01L24/05 ,  H01L24/03 ,  H01L24/45 ,  H01L24/85 ,  H01L2224/02165 ,  H01L2224/03013 ,  H01L2224/04042 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05181 ,  H01L2224/05186 ,  H01L2224/05644 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/85

摘要： A pad electrode is formed in an uppermost wiring layer of a multilayer wiring layer formed on a semiconductor substrate. A dielectric film is formed to cover the pad electrode. An opening portion is formed in the dielectric film so as to reach the pad electrode. In the opening portion, a conductive film that is a part of a conductive layer is electrically connected to the pad electrode. On a side surface of the conductive film, an oxide layer in which a material contained in the conductive film is oxidized is formed. A width of the oxide layer is 200 nm or more.

公开(公告)号：US20170084560A1

公开(公告)日：2017-03-23

申请号：US15369586

申请日：2016-12-05

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chen-Hua Yu ,  Hao-Yi Tsai ,  Chien-Hsun Lee ,  Chung-Shi Liu ,  Hsien-Wei Chen

IPC分类号： H01L23/00

CPC分类号： H01L24/11 ,  H01L24/02 ,  H01L24/05 ,  H01L24/13 ,  H01L24/14 ,  H01L2224/02125 ,  H01L2224/02165 ,  H01L2224/02335 ,  H01L2224/0239 ,  H01L2224/024 ,  H01L2224/03464 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05024 ,  H01L2224/05027 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05562 ,  H01L2224/05567 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/05669 ,  H01L2224/1132 ,  H01L2224/1134 ,  H01L2224/11849 ,  H01L2224/13022 ,  H01L2224/13026 ,  H01L2224/13076 ,  H01L2224/13078 ,  H01L2224/13082 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/1403 ,  H01L2224/14051 ,  H01L2224/14131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/06 ,  H01L2924/351 ,  H01L2924/3512 ,  H01L2224/05552 ,  H01L2924/00

摘要： Methods and apparatus for solder connections. An apparatus includes a substrate having a conductive terminal on a surface; a passivation layer overlying the surface of the substrate and the conductive terminal; an opening in the passivation layer exposing a portion of the conductive terminal; at least one stud bump bonded to the conductive terminal in the opening and extending in a direction normal to the surface of the substrate; and a solder connection formed on the conductive terminal in the opening and enclosing the at least one stud bump. Methods for forming the solder connections are disclosed.

公开(公告)号：US20130249105A1

公开(公告)日：2013-09-26

申请号：US13426552

申请日：2012-03-21

申请人： Yaojian Lin ,  Kang Chen

发明人： Yaojian Lin ,  Kang Chen

IPC分类号： H01L23/522 ,  H01L21/768

CPC分类号： H01L23/562 ,  H01L21/561 ,  H01L23/3157 ,  H01L23/5226 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L2224/02125 ,  H01L2224/02165 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/0346 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/05552 ,  H01L2224/05557 ,  H01L2224/05559 ,  H01L2224/05567 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/10126 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1145 ,  H01L2224/1146 ,  H01L2224/11849 ,  H01L2224/11901 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/01082 ,  H01L2924/014

摘要： A semiconductor device has a semiconductor die and first insulating layer formed over the semiconductor die. A plurality of first micro-vias can be formed in the first insulating layer. A conductive layer is formed in the first micro-openings and over the first insulating layer. A second insulating layer is formed over the first insulating layer and conductive layer. A portion of the second insulating layer is removed to expose the conductive layer and form a plurality of second micro-openings in the second insulating layer over the conductive layer. The second micro-openings can be micro-vias, micro-via ring, or micro-via slots. Removing the portion of the second insulating layer leaves an island of the second insulating layer over the conductive layer. A bump is formed over the conductive layer. A third insulating layer is formed in the second micro-openings over the bump. The second micro-openings provide stress relief.

摘要翻译： 半导体器件具有形成在半导体管芯上的半导体管芯和第一绝缘层。 可以在第一绝缘层中形成多个第一微通孔。 导电层形成在第一微孔中并在第一绝缘层之上。 在第一绝缘层和导电层上形成第二绝缘层。 去除第二绝缘层的一部分以暴露导电层并在导电层上的第二绝缘层中形成多个第二微孔。 第二微孔可以是微通孔，微通孔环或微通孔。 去除第二绝缘层的部分在导电层上留下第二绝缘层的岛。 在导电层上形成凸点。 在凸起上的第二微孔中形成第三绝缘层。 第二个微孔提供应力消除。