公开(公告)号：US20120228263A1

公开(公告)日：2012-09-13

申请号：US13424952

申请日：2012-03-20

申请人： Akio UI ,  Hisataka Hayashi ,  Keisuke Kikutani

发明人： Akio UI ,  Hisataka Hayashi ,  Keisuke Kikutani

IPC分类号： B44C1/22 ,  B05C9/00

CPC分类号： H01L21/31116 ,  H01J37/32091 ,  H01J37/32146 ,  H01J37/32174

摘要： In one embodiment, a substrate processing apparatus, includes: a chamber; a first electrode disposed in the chamber; a second electrode disposed in the chamber to face the first electrode, and to hold a substrate; an RF power supply to apply an RF voltage with a frequency of 50 MHz or more to the second electrode; and a pulse power supply to repeatedly apply a voltage waveform including a negative voltage pulse and a positive voltage pulse of which delay time from the negative voltage pulse is 50 nano-seconds or less to the second electrode while superposing on the RF voltage.

摘要翻译： 在一个实施例中，基板处理装置包括：腔室; 设置在所述室中的第一电极; 设置在所述腔室中以面对所述第一电极并且保持衬底的第二电极; RF电源，向第二电极施加频率为50MHz以上的RF电压; 以及脉冲电源，用于在叠加在RF电压上的同时，将包括负电压脉冲和负电压脉冲的延迟时间的正电压脉冲的电压波形重复地施加到第二电极50纳秒以下。

公开(公告)号：US09583360B2

公开(公告)日：2017-02-28

申请号：US13424952

申请日：2012-03-20

申请人： Akio Ui ,  Hisataka Hayashi ,  Keisuke Kikutani

发明人： Akio Ui ,  Hisataka Hayashi ,  Keisuke Kikutani

IPC分类号： C23C16/00 ,  C23F1/00 ,  H01L21/306 ,  H01L21/311 ,  H01J37/32

CPC分类号： H01L21/31116 ,  H01J37/32091 ,  H01J37/32146 ,  H01J37/32174

摘要： In one embodiment, a substrate processing apparatus, includes: a chamber; a first electrode disposed in the chamber; a second electrode disposed in the chamber to face the first electrode, and to hold a substrate; an RF power supply to apply an RF voltage with a frequency of 50 MHz or more to the second electrode; and a pulse power supply to repeatedly apply a voltage waveform including a negative voltage pulse and a positive voltage pulse of which delay time from the negative voltage pulse is 50 nano-seconds or less to the second electrode while superposing on the RF voltage.

摘要翻译： 在一个实施例中，基板处理装置包括：腔室; 设置在所述室中的第一电极; 设置在所述腔室中以面对所述第一电极并且保持衬底的第二电极; RF电源，向第二电极施加频率为50MHz以上的RF电压; 以及脉冲电源，用于在叠加在RF电压上的同时，将包括负电压脉冲和负电压脉冲的延迟时间的正电压脉冲的电压波形重复地施加到第二电极50纳秒以下。

公开(公告)号：US20100304568A1

公开(公告)日：2010-12-02

申请号：US12752684

申请日：2010-04-01

申请人： Seiro MIYOSHI ,  Yasunobu Kai ,  Kentaro Matsunaga ,  Keisuke Kikutani ,  Eishi Shiobara ,  Shinya Takahashi

发明人： Seiro MIYOSHI ,  Yasunobu Kai ,  Kentaro Matsunaga ,  Keisuke Kikutani ,  Eishi Shiobara ,  Shinya Takahashi

IPC分类号： H01L21/302 ,  G03F7/20

CPC分类号： G03F1/34 ,  G03F7/095 ,  H01L21/0274 ,  H01L21/31144

摘要： A pattern forming method includes forming a first photoresist on an underlying region, forming a second photoresist on the first photoresist, the second photoresist having an exposure sensitivity which is different from an exposure sensitivity of the first photoresist, radiating exposure light on the first and second photoresists via a photomask including a first transmissive region and a second transmissive region which cause a phase difference of 180° between transmissive light components passing therethrough, the first transmissive region and the second transmissive region being provided in a manner to neighbor in an irradiation region, and developing the first and second photoresists which have been irradiated with the exposure light, thereby forming a structure includes a first region where the underlying region is exposed, a second region where the first photoresist is exposed and a third region where the first photoresist and the second photoresist are left.

摘要翻译： 图案形成方法包括在下面的区域上形成第一光致抗蚀剂，在第一光致抗蚀剂上形成第二光致抗蚀剂，第二光致抗蚀剂具有不同于第一光致抗蚀剂的曝光灵敏度的曝光灵敏度， 通过包括第一透射区域和第二透射区域的光掩模进行光刻，所述第一透射区域和第二透射区域在穿过其中的透射光分量之间产生180°的相位差，第一透射区域和第二透射区域以照射区域相邻的方式设置， 以及显影已经用曝光光照射的第一和第二光致抗蚀剂，由此形成结构，其包括下部区域被暴露的第一区域，第一光致抗蚀剂被曝光的第二区域和第一光致抗蚀剂 剩下第二光致抗蚀剂。

公开(公告)号：US07749913B2

公开(公告)日：2010-07-06

申请号：US12336348

申请日：2008-12-16

申请人： Mitsuhiro Omura ,  Keisuke Kikutani ,  Yutaka Okamoto

发明人： Mitsuhiro Omura ,  Keisuke Kikutani ,  Yutaka Okamoto

IPC分类号： H01L21/302

CPC分类号： H01L21/31144 ,  H01L21/0337 ,  H01L21/31116 ,  H01L21/31138

摘要： A first silicon containing film, an organic material film, a second silicon containing film are formed. The second silicon containing film is patterned to have a narrow width pattern and a wide width pattern. The organic material film is patterned to have a narrow width pattern and a wide width pattern. A side wall is formed on a side surface of the second silicon containing film and the organic material film by coating with a third silicon containing film. The narrow width pattern of the second silicon containing film is removed by using a mask that covers the second silicon containing film patterned to have a wide width pattern and the side wall. Finally, the organic material film is removed.

摘要翻译： 形成第一含硅膜，有机材料膜，第二含硅膜。 将第二含硅膜图案化为具有窄的宽度图案和宽的宽度图案。 有机材料膜被图案化以具有窄的宽度图案和宽的宽度图案。 通过涂覆第三含硅膜，在第二含硅膜和有机材料膜的侧表面上形成侧壁。 通过使用覆盖图案化的第二含硅膜具有宽幅图案和侧壁的掩模来除去第二含硅膜的窄幅图案。 最后，除去有机材料膜。

公开(公告)号：US20080045026A1

公开(公告)日：2008-02-21

申请号：US11892131

申请日：2007-08-20

申请人： Keisuke Kikutani

发明人： Keisuke Kikutani

IPC分类号： H01L21/461

CPC分类号： H01L21/31111 ,  H01L21/0273 ,  H01L21/0332 ,  H01L21/32139

摘要： A method for manufacturing a semiconductor device includes forming a photo-resist pattern above a first film, implanting a predetermined dopant that increases an etching rate of the first film into the first film using the photo-resist pattern as a mask, thereby forming an implantation layer in the first film, and etching a first portion of the first film, which is at least a part of the implantation layer, using the photo-resist pattern as a mask.

摘要翻译： 一种制造半导体器件的方法包括在第一膜上形成光致抗蚀剂图案，使用光致抗蚀剂图案作为掩模，将预定的掺杂剂注入第一膜的蚀刻速率，从而形成植入 层，并且使用光致抗蚀剂图案作为掩模来蚀刻作为注入层的至少一部分的第一膜的第一部分。

公开(公告)号：US08975178B2

公开(公告)日：2015-03-10

申请号：US13602841

申请日：2012-09-04

申请人： Keisuke Kikutani ,  Satoshi Nagashima ,  Hidefumi Mukai ,  Takehiro Kondoh ,  Hisataka Meguro

发明人： Keisuke Kikutani ,  Satoshi Nagashima ,  Hidefumi Mukai ,  Takehiro Kondoh ,  Hisataka Meguro

IPC分类号： H01L21/4763 ,  H01L21/768 ,  H01L21/033 ,  H01L21/3213 ,  H01L27/115

CPC分类号： H01L21/76801 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/32139 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11548 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11575

摘要： According to one embodiment, a method of manufacturing a device, includes forming a first core including a line portion extending between first and second regions and having a first width and a fringe having a dimension larger than the first width, forming a mask on the fringe and on a first sidewall on the first core, removing the first core so that a remaining portion having a dimension larger than the first width is formed below the mask, forming a second sidewall on a pattern corresponding the first sidewall and the remaining portion, the second sidewall having a second width less than the first width and facing a first interval less than the first width in the first region and facing a second interval larger than the first interval in the second region.

摘要翻译： 根据一个实施例，一种制造器件的方法包括形成包括在第一和第二区域之间延伸的线部分并具有第一宽度和具有大于第一宽度的尺寸的条纹的第一芯体，在边缘上形成掩模 并且在所述第一芯上的第一侧壁上，移除所述第一芯，使得具有大于所述第一宽度的尺寸的剩余部分形成在所述掩模下方，在对应于所述第一侧壁和所述剩余部分的图案上形成第二侧壁， 第二侧壁具有小于第一宽度的第二宽度并且面向小于第一区域中的第一宽度的第一间隔并且面向大于第二区域中的第一间隔的第二间隔。

公开(公告)号：US08785327B2

公开(公告)日：2014-07-22

申请号：US13603887

申请日：2012-09-05

申请人： Keisuke Kikutani

发明人： Keisuke Kikutani

IPC分类号： H01L21/3213 ,  H01L21/027

CPC分类号： H01L21/308 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/32139 ,  H01L21/768 ,  H01L27/0207 ,  H01L27/11519 ,  H01L27/11529 ,  H01L27/11548 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575

摘要： According to one embodiment, a method of manufacturing a semiconductor device, includes forming first layer on first and second regions in substrate, first layer having first width in first region and having larger dimension than first width in second region, forming first sidewall on first layer, forming second layer covering first sidewall in the second region and forming third layer having second width smaller than first width on the side face of first sidewall having second width after removing first layer, forming second and third sidewalls having second width so that second and third sidewalls is adjacent to first sidewall across third layer by second width in first region and across second and third layers by second interval larger than second width in the second region.

摘要翻译： 根据一个实施例，制造半导体器件的方法包括在衬底中的第一和第二区域上形成第一层，第一层在第一区域具有第一宽度并且具有比第二区域中的第一宽度更大的尺寸，在第一层上形成第一侧壁 在第二区域中形成覆盖第一侧壁的第二层，并且在去除第一层之后，在具有第二宽度的第一侧壁的侧面上形成具有小于第一宽度的第二宽度的第三层，形成具有第二宽度的第二和第三侧壁，使得第二和第三 侧壁在第一区域中跨越第三层与第一侧壁相邻第二宽度，并且在第二区域中跨越第二和第三层延伸大于第二宽度的第二间隔。

公开(公告)号：US20110117745A1

公开(公告)日：2011-05-19

申请号：US12881283

申请日：2010-09-14

申请人： Koichi SATO ,  Keisuke Kikutani

发明人： Koichi SATO ,  Keisuke Kikutani

IPC分类号： H01L21/302

CPC分类号： H01L21/32139 ,  H01L21/0337 ,  H01L21/0338

摘要： A method of manufacturing a semiconductor device according to an embodiment includes processing a second film 14 formed on a semiconductor substrate to a pattern including a plurality of linear parts and end portions formed in an end of each of the linear parts, having a width wider than the linear parts, forming a first pattern 16 by slimming the pattern, forming a second pattern including a first opening 180 that traverses the end portion 141a of the first pattern 16, etching the second film 14 exposed in the first opening 180, and dividing the end portion 141a into a first end portion 142a close to the linear part 140a and a second end portion 143a apart from the linear part 140a.

摘要翻译： 根据实施例的制造半导体器件的方法包括将形成在半导体衬底上的第二膜14处理成包括形成在每个直线部分的端部中的多个直线部分和端部的图案，其宽度大于 线状部件，通过使图案减薄形成第一图案16，形成包括穿过第一图案16的端部141a的第一开口180的第二图案，蚀刻暴露在第一开口180中的第二膜14， 端部141a形成靠近直线部140a的第一端部142a和与直线部140a分离的第二端部143a。

公开(公告)号：US07923375B2

公开(公告)日：2011-04-12

申请号：US11892131

申请日：2007-08-20

申请人： Keisuke Kikutani

发明人： Keisuke Kikutani

IPC分类号： H01L21/302

CPC分类号： H01L21/31111 ,  H01L21/0273 ,  H01L21/0332 ,  H01L21/32139

摘要： A method for manufacturing a semiconductor device includes forming a photo-resist pattern above a first film, implanting a predetermined dopant that increases an etching rate of the first film into the first film using the photo-resist pattern as a mask, thereby forming an implantation layer in the first film, and etching a first portion of the first film, which is at least a part of the implantation layer, using the photo-resist pattern as a mask.

摘要翻译： 一种制造半导体器件的方法包括在第一膜上形成光致抗蚀剂图案，使用光致抗蚀剂图案作为掩模，将预定的掺杂物注入第一膜的蚀刻速率，从而形成植入 层，并且使用光致抗蚀剂图案作为掩模来蚀刻作为注入层的至少一部分的第一膜的第一部分。

公开(公告)号：US20090221147A1

公开(公告)日：2009-09-03

申请号：US12395094

申请日：2009-02-27

申请人： Keisuke Kikutani ,  Katsunori Yahashi

发明人： Keisuke Kikutani ,  Katsunori Yahashi

IPC分类号： H01L21/306

CPC分类号： H01L21/0337 ,  H01L21/0338 ,  H01L21/31144 ,  H01L21/32139 ,  Y10S438/947

摘要： A method of fabricating a semiconductor device according to an embodiment includes: forming a core material on a workpiece material; forming a cover film to cover the upper and side surfaces of the core material; after forming the cover film, removing the core material; after removing the core material, removing the cover film while leaving portions thereof located on the side surfaces of the core material, so as to form sidewall spacer masks; and etching the workpiece material by using the sidewall spacer masks as a mask.

摘要翻译： 根据实施例的制造半导体器件的方法包括：在工件材料上形成芯材; 形成覆盖所述芯材的上表面和侧表面的覆盖膜; 在形成覆盖膜之后，去除芯材; 在去除芯材之后，移除覆盖膜，同时留下位于芯材侧表面的部分，以便形成侧壁间隔物掩模; 并且通过使用侧壁间隔物掩模作为掩模来蚀刻工件材料。