公开(公告)号：US08253182B2

公开(公告)日：2012-08-28

申请号：US12588203

申请日：2009-10-07

申请人： Minori Kajimoto ,  Mitsuhiro Noguchi ,  Akira Goda

发明人： Minori Kajimoto ,  Mitsuhiro Noguchi ,  Akira Goda

IPC分类号： H01L29/76

CPC分类号： H01L27/11568 ,  H01L21/76838 ,  H01L27/115 ,  H01L27/11521

摘要： A nonvolatile semiconductor memory includes a first semiconductor layer; second semiconductor regions formed on the first semiconductor layer having device isolating regions extended in a column direction; a first interlayer insulator film formed above the first semiconductor layer; a lower conductive plug connected to the second semiconductor regions; a first interconnect extended in a row direction; a second interlayer insulator formed on the lower conductive plug and the first interlayer insulator film; an upper conductive plug; and a second interconnect formed on the second interlayer insulator contacting with the top of the upper conductive plug extended in the column direction.

摘要翻译： 非易失性半导体存储器包括：第一半导体层; 形成在第一半导体层上的第二半导体区域，具有沿列方向延伸的器件隔离区域; 形成在所述第一半导体层上方的第一层间绝缘膜; 连接到第二半导体区域的下导电插塞; 沿行方向延伸的第一互连; 形成在下导电插塞和第一层间绝缘膜上的第二层间绝缘膜; 上导电插头; 以及形成在与沿列方向延伸的上导电插塞的顶部接触的第二层间绝缘体上的第二互连。

公开(公告)号：US07372113B2

公开(公告)日：2008-05-13

申请号：US10880508

申请日：2004-07-01

申请人： Masayuki Tanaka ,  Yoshio Ozawa ,  Shigehiko Saida ,  Akira Goda ,  Mitsuhiro Noguchi ,  Yuichiro Mitani ,  Yoshitaka Tsunashima

发明人： Masayuki Tanaka ,  Yoshio Ozawa ,  Shigehiko Saida ,  Akira Goda ,  Mitsuhiro Noguchi ,  Yuichiro Mitani ,  Yoshitaka Tsunashima

IPC分类号： H01L21/314

CPC分类号： H01L21/022 ,  H01L21/0217 ,  H01L21/28176 ,  H01L21/28202 ,  H01L21/28247 ,  H01L21/28282 ,  H01L21/28518 ,  H01L21/3185 ,  H01L21/76838 ,  H01L21/76897 ,  H01L29/513 ,  H01L29/518 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/792

摘要： Disclosed is a semiconductor device comprising a semiconductor substrate, a gate electrode, a first insulating film formed between the semiconductor substrate and the gate electrode, and a second insulating film formed along a top surface or a side surface of the gate electrode and including a lower silicon nitride film containing nitrogen, silicon and hydrogen and an upper silicon nitride film formed on the lower silicon nitride film and containing nitrogen, silicon and hydrogen, and wherein a composition ratio N/Si of nitrogen (N) to silicon (Si) in the lower silicon nitride film is higher than that in the upper silicon nitride film.

摘要翻译： 公开了一种半导体器件，包括半导体衬底，栅电极，形成在半导体衬底和栅电极之间的第一绝缘膜，以及沿着栅电极的顶表面或侧表面形成的第二绝缘膜， 包含氮，硅和氢的氮化硅膜和形成在下部氮化硅膜上并含有氮，硅和氢的上部氮化硅膜，并且其中氮（N）与硅（Si）的组成比N / Si在 下氮化硅膜比上述氮化硅膜高。

公开(公告)号：US07326993B2

公开(公告)日：2008-02-05

申请号：US10890132

申请日：2004-07-14

申请人： Minori Kajimoto ,  Mitsuhiro Noguchi ,  Akira Goda

发明人： Minori Kajimoto ,  Mitsuhiro Noguchi ,  Akira Goda

IPC分类号： H01L29/788 ,  H01L23/522

CPC分类号： H01L27/11568 ,  H01L21/76838 ,  H01L27/115 ,  H01L27/11521

摘要： A nonvolatile semiconductor memory includes a first semiconductor layer; second semiconductor regions formed on the first semiconductor layer having device isolating regions extended in a column direction; a first interlayer insulator film formed above the first semiconductor layer; a lower conductive plug connected to the second semiconductor regions; a first interconnect extended in a row direction; a second interlayer insulator formed on the lower conductive plug and the first interlayer insulator film; an upper conductive plug; and a second interconnect formed on the second interlayer insulator contacting with the top of the upper conductive plug extended in the column direction.

公开(公告)号：US07006379B2

公开(公告)日：2006-02-28

申请号：US11068228

申请日：2005-03-01

申请人： Mitsuhiro Noguchi ,  Akira Goda ,  Yasuhiko Matsunaga

发明人： Mitsuhiro Noguchi ,  Akira Goda ,  Yasuhiko Matsunaga

IPC分类号： G11C16/04

CPC分类号： G11C16/26 ,  G11C16/0483 ,  H01L27/115

摘要： A semiconductor memory including a memory cell unit, the memory cell unit comprising: a plurality of memory cells in which each conductance between current terminals changes according to held data, each having a plurality of current terminals connected in series between a first terminal and a second terminal, and each capable of electrically rewriting the data; a first select switching element electrically connecting said first terminal to a data transfer line; and a MISFET serving as a second select switching element connecting said second terminal to a reference potential line, wherein said semiconductor memory has a data read mode for forcing the first and second select switching elements of said memory cell unit into conduction, applying a read voltage for forcing a path between the current terminals into conduction or cut-off according to the data of a selected memory cell, to a control electrode of the selected memory cell, applying a pass voltage for forcing a path between the current terminals into conduction irrespectively of the data of each of the memory cells other than said selected memory cell, to the control electrode of each of the memory cells other than said selected memory cell, and detecting presence and absence or magnitude of a current between said data transfer line and said reference potential line, and in said data read mode, a conductance between current terminals of said MISFET is set lower than a conductance, in the case where the conductance between the current terminals is set to be the lowest, with regards to at least one of the memory cells other than said selected memory cell.

摘要翻译： 一种包括存储单元单元的半导体存储器，所述存储单元单元包括：多个存储单元，其中当前端子之间的每个电导根据保持的数据而改变，每个存储单元具有串联连接在第一端子和第二端子之间的多个电流端子 终端，并且每个都能够电气地重写数据; 将所述第一端子电连接到数据传输线路的第一选择开关元件; 以及用作将所述第二端子连接到参考电位线的第二选择开关元件的MISFET，其中所述半导体存储器具有用于将所述存储单元单元的第一和第二选择开关元件强制为导通的数据读取模式，施加读取电压 用于根据所选择的存储单元的数据将当前端子之间的路径强制为导通或截止，到所选存储单元的控制电极，施加通过电压，以迫使当前端子之间的路径导通，而不管 除了所述选择的存储单元之外的每个存储单元的数据，还包括除了所选择的存储单元之外的每个存储单元的控制电极，以及检测所述数据传输线与所述参考电压之间的电流的存在和否定 电位线，并且在所述数据读取模式中，将所述MISFET的电流端子之间的电导设置为低于电导， 关于当前终端之间的电导被设置为最低的情况，关于除了所选择的存储单元之外的至少一个存储单元。

公开(公告)号：US06958938B2

公开(公告)日：2005-10-25

申请号：US11007461

申请日：2004-12-09

申请人： Mitsuhiro Noguchi ,  Akira Goda ,  Yuji Takeuchi

发明人： Mitsuhiro Noguchi ,  Akira Goda ,  Yuji Takeuchi

IPC分类号： G11C16/02 ,  G11C16/04 ,  G11C16/06 ,  G11C16/10 ,  G11C16/12 ,  G11C16/34 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： G11C16/3445 ,  G11C16/0416 ,  G11C16/0483 ,  G11C16/12 ,  G11C16/3468

摘要： A data writing method for a semiconductor memory device includes writing data into the first memory cell, rewriting the data into the first memory cell when an insufficiency of the data of the first memory cell is determined as a result of verifying the data of the first memory cell at one first reference threshold voltage, writing data into the second memory cell following writing the data into the first memory cell, and rewriting the data into the first memory cell following writing the data into the second memory cell when an insufficiency of the data of the first memory cell is determined as a result of verifying the data of the first memory cell at one second reference threshold voltage. The first reference threshold voltage is set to be different from the second reference threshold voltage.

摘要翻译： 半导体存储器件的数据写入方法包括将数据写入第一存储单元，当确定第一存储单元的数据不足时，将数据重新写入第一存储器单元作为验证第一存储器的数据的结果 在一个第一参考阈值电压下，将数据写入第一存储单元之后，将数据写入第二存储单元，并且当数据不足时将数据写入第二存储单元中 作为第一存储单元的数据在一秒钟的参考阈值电压下进行验证的结果来确定第一存储单元。 第一参考阈值电压被设置为不同于第二参考阈值电压。

公开(公告)号：US06925009B2

公开(公告)日：2005-08-02

申请号：US10920355

申请日：2004-08-18

申请人： Mitsuhiro Noguchi ,  Akira Goda ,  Yasuhiko Matsunaga

发明人： Mitsuhiro Noguchi ,  Akira Goda ,  Yasuhiko Matsunaga

IPC分类号： G11C16/06 ,  G11C16/04 ,  G11C16/26 ,  H01L21/8247 ,  H01L27/10 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： G11C16/26 ,  G11C16/0483 ,  H01L27/115

摘要： A semiconductor memory including a memory cell unit, the memory cell unit comprising: a plurality of memory cells in which each conductance between current terminals changes according to held data, each having a plurality of current terminals connected in series between a first terminal and a second terminal, and each capable of electrically rewriting the data; a first select switching element electrically connecting said first terminal to a data transfer line; and a MISFET serving as a second select switching element connecting said second terminal to a reference potential line, wherein said semiconductor memory has a data read mode for forcing the first and second select switching elements of said memory cell unit into conduction, applying a read voltage for forcing a path between the current terminals into conduction or cut-off according to the data of a selected memory cell, to a control electrode of the selected memory cell, applying a pass voltage for forcing a path between the current terminals into conduction irrespectively of the data of each of the memory cells other than said selected memory cell, to the control electrode of each of the memory cells other than said selected memory cell, and detecting presence and absence or magnitude of a current between said data transfer line and said reference potential line, and in said data read mode, a conductance between current terminals of said MISFET is set lower than a conductance, in the case where the conductance between the current terminals is set to be the lowest, with regards to at least one of the memory cells other than said selected memory cell.

摘要翻译： 一种包括存储单元单元的半导体存储器，所述存储单元单元包括：多个存储单元，其中当前端子之间的每个电导根据保持的数据而改变，每个存储单元具有串联连接在第一端子和第二端子之间的多个电流端子 终端，并且每个都能够电气地重写数据; 将所述第一端子电连接到数据传输线路的第一选择开关元件; 以及用作将所述第二端子连接到参考电位线的第二选择开关元件的MISFET，其中所述半导体存储器具有用于将所述存储单元单元的第一和第二选择开关元件强制为导通的数据读取模式，施加读取电压 用于根据所选择的存储单元的数据将当前端子之间的路径强制为导通或截止，到所选存储单元的控制电极，施加通过电压，以迫使当前端子之间的路径导通，而不管 除了所述选择的存储单元之外的每个存储单元的数据，还包括除了所选择的存储单元之外的每个存储单元的控制电极，以及检测所述数据传输线与所述参考电压之间的电流的存在和否定 电位线，并且在所述数据读取模式中，将所述MISFET的电流端子之间的电导设置为低于电导， 关于当前终端之间的电导被设置为最低的情况，关于除了所选择的存储单元之外的至少一个存储单元。

公开(公告)号：US20050157578A1

公开(公告)日：2005-07-21

申请号：US11074801

申请日：2005-03-09

申请人： Mitsuhiro Noguchi ,  Akira Goda ,  Hiroyuki Nitta

发明人： Mitsuhiro Noguchi ,  Akira Goda ,  Hiroyuki Nitta

IPC分类号： G11C16/02 ,  G06F11/10 ,  G11C8/00 ,  G11C11/34 ,  G11C16/00 ,  G11C16/04 ,  G11C16/06 ,  G11C16/10 ,  G11C16/26 ,  G11C16/32 ,  G11C16/34 ,  G11C29/00 ,  G11C29/04 ,  G11C29/42 ,  G11C29/52 ,  H01L21/8247 ,  H01L27/00 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： G06F11/1008 ,  G06F11/108 ,  G11C7/22 ,  G11C16/04 ,  G11C16/0483 ,  G11C16/26 ,  G11C16/32 ,  G11C16/3454 ,  G11C29/50004 ,  G11C29/52 ,  G11C29/76 ,  G11C29/82 ,  G11C29/84 ,  G11C2029/0409 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524

摘要： A semiconductor memory device includes: a memory cell array having a plurality of data select lines disposed in parallel with each other, a plurality of data transfer line disposed in parallel with each other to intersect the data select lines, and electrically rewritable memory cells laid out at cross portions between the data select lines and data transfer lines; a data select line driver for driving the data select lines of the memory cell array; a sense amplifier circuit connected to the data transfer lines of the memory cell array, for performing data read of memory cells selected by one of the data select lines; and a control circuit used for timing control of data read of the memory cell array, for outputting at least two types of timing signals as being different in accordance with a selected data area of the memory cell array.

公开(公告)号：US20050093047A1

公开(公告)日：2005-05-05

申请号：US10954238

申请日：2004-10-01

申请人： Akira Goda ,  Mitsuhiro Noguchi

发明人： Akira Goda ,  Mitsuhiro Noguchi

IPC分类号： H01L21/8247 ,  H01L21/8246 ,  H01L27/00 ,  H01L27/105 ,  H01L27/108 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L27/115 ,  H01L27/105 ,  H01L27/11568 ,  H01L27/11573

摘要： A semiconductor memory device having a memory cell region and a peripheral circuit region, and a method of manufacturing such a semiconductor memory device, are proposed, in which trench grooves are formed to be shallow in the memory cell region in order to improve the yield, and trench grooves are formed to be deep in the high voltage transistor region of the peripheral circuit region, in particular in a high voltage transistor region thereof, in order to improve the element isolation withstand voltage. A plurality of memory cell transistors having an ONO layer 15 serving as a charge accumulating insulating layer are provided in the memory cell region, where element isolation grooves 6 for these memory cell transistors are narrow and shallow. Two types of transistors, one for high voltage and the other for low voltage, having gate insulating layers 16 or 17, which are different from the ONO layer 15 in the memory cell region, are provided in the peripheral circuit region, where at least element isolation grooves 23 for high voltage transistors are wide and deep. In this way, it is possible to improve the degree of integration and yield in the memory cell region, and secure withstand voltage in the peripheral circuit region.

摘要翻译： 提出了具有存储单元区域和外围电路区域的半导体存储器件以及制造这种半导体存储器件的方法，其中沟槽形成在存储单元区域中较浅以提高产量， 并且在周边电路区域的高电压晶体管区域，特别是在其高压晶体管区域中形成深沟槽，以便提高元件隔离耐受电压。 在存储单元区域中设置有多个具有作为电荷累积绝缘层的ONO层15的存储单元晶体管，其中用于这些存储单元晶体管的元件隔离槽6窄而浅。 在外围电路区域中设置两个类型的晶体管，一个用于高电压，另一个用于低电压，具有与存储单元区域中的ONO层15不同的栅极绝缘层16或17，其中至少元件 用于高压晶体管的隔离槽23宽而深。 以这种方式，可以提高存储单元区域的集成度和产量，并且确保外围电路区域中的耐受电压。

公开(公告)号：US20050045941A1

公开(公告)日：2005-03-03

申请号：US10893295

申请日：2004-07-19

申请人： Koichi Kurita ,  Mitsuhiro Noguchi ,  Akira Goda

发明人： Koichi Kurita ,  Mitsuhiro Noguchi ,  Akira Goda

IPC分类号： G11C17/00 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L27/11524 ,  H01L29/42324

摘要： According to the present invention, there is provided a nonvolatile semiconductor memory capable of electrically writing and erasing information, comprising: a semiconductor substrate; source and drain regions formed at a predetermined spacing in a surface portion of said semiconductor substrate; a channel region positioned between said source and drain regions; a floating gate electrode formed on said cannel region via a first insulating film; a control gate electrode including a semiconductor layer formed on said floating gate electrode via a second insulating film, and a metal layer formed on said semiconductor layer; and an oxidation-resistant third insulating film formed on said control gate electrode, wherein the nonvolatile semiconductor memory further comprises an oxidation-resistant fourth insulating film so formed as to cover at least sidewalls of said metal layer, and said fourth insulating film is formed from the sidewalls of said metal layer to at least portions of sidewalls of said semiconductor layer of said control gate electrode.

摘要翻译： 根据本发明，提供一种能够电写入和擦除信息的非易失性半导体存储器，包括：半导体衬底; 在所述半导体衬底的表面部分中以预定间隔形成的源区和漏区; 位于所述源区和漏区之间的沟道区; 经由第一绝缘膜形成在所述槽区上的浮栅电极; 包括经由第二绝缘膜形成在所述浮置栅电极上的半导体层的控制栅电极和形成在所述半导体层上的金属层; 以及形成在所述控制栅电极上的抗氧化的第三绝缘膜，其中所述非易失性半导体存储器还包括形成为至少覆盖所述金属层的侧壁的耐氧化的第四绝缘膜，并且所述第四绝缘膜由 所述金属层的侧壁至所述控制栅电极的所述半导体层的侧壁的至少部分。

公开(公告)号：US20050018485A1

公开(公告)日：2005-01-27

申请号：US10920355

申请日：2004-08-18

申请人： Mitsuhiro Noguchi ,  Akira Goda ,  Yasuhiko Matsunaga

发明人： Mitsuhiro Noguchi ,  Akira Goda ,  Yasuhiko Matsunaga

IPC分类号： G11C16/06 ,  G11C16/04 ,  G11C16/26 ,  H01L21/8247 ,  H01L27/10 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C11/34

CPC分类号： G11C16/26 ,  G11C16/0483 ,  H01L27/115

摘要： A semiconductor memory including a memory cell unit, the memory cell unit comprising: a plurality of memory cells in which each conductance between current terminals changes according to held data, each having a plurality of current terminals connected in series between a first terminal and a second terminal, and each capable of electrically rewriting the data; a first select switching element electrically connecting said first terminal to a data transfer line; and a MISFET serving as a second select switching element connecting said second terminal to a reference potential line, wherein said semiconductor memory has a data read mode for forcing the first and second select switching elements of said memory cell unit into conduction, applying a read voltage for forcing a path between the current terminals into conduction or cut-off according to the data of a selected memory cell, to a control electrode of the selected memory cell, applying a pass voltage for forcing a path between the current terminals into conduction irrespectively of the data of each of the memory cells other than said selected memory cell, to the control electrode of each of the memory cells other than said selected memory cell, and detecting presence and absence or magnitude of a current between said data transfer line and said reference potential line, and in said data read mode, a conductance between current terminals of said MISFET is set lower than a conductance, in the case where the conductance between the current terminals is set to be the lowest, with regards to at least one of the memory cells other than said selected memory cell.

摘要翻译： 一种包括存储单元单元的半导体存储器，所述存储单元单元包括：多个存储单元，其中当前端子之间的每个电导根据保持的数据而改变，每个存储单元具有串联连接在第一端子和第二端子之间的多个电流端子 终端，并且每个都能够电气地重写数据; 将所述第一端子电连接到数据传输线路的第一选择开关元件; 以及用作将所述第二端子连接到参考电位线的第二选择开关元件的MISFET，其中所述半导体存储器具有用于将所述存储单元单元的第一和第二选择开关元件强制为导通的数据读取模式，施加读取电压 用于根据所选择的存储单元的数据将当前端子之间的路径强制为导通或截止，到所选存储单元的控制电极，施加通过电压，以迫使当前端子之间的路径导通，而不管 除了所述选择的存储单元之外的每个存储单元的数据，还包括除了所选择的存储单元之外的每个存储单元的控制电极，以及检测所述数据传输线与所述参考电压之间的电流的存在和否定 电位线，并且在所述数据读取模式中，将所述MISFET的电流端子之间的电导设置为低于电导， 关于当前终端之间的电导被设置为最低的情况，关于除了所选择的存储单元之外的至少一个存储单元。