公开(公告)号：US06342420B1

公开(公告)日：2002-01-29

申请号：US09542002

申请日：2000-04-03

申请人： Akitoshi Nishimura ,  Yasutoshi Okuno ,  Rajesh Khamankar ,  Shane R. Palmer

发明人： Akitoshi Nishimura ,  Yasutoshi Okuno ,  Rajesh Khamankar ,  Shane R. Palmer

IPC分类号： H01L218242

CPC分类号： H01L27/10888 ,  H01L27/10805 ,  Y10S257/905

摘要： An apparatus and method for fabrication a hexagonally symmetric cell, (e.g., a dynamic random access memory cell (100)). The cell can comprise a bitline contact (38), storage node contacts (32) hexagonally surrounding the bitline contact (38), storage nodes (36) also surrounding the bitline contact (38), a wordline (30) portions of which form field effect transistor gates. Large distances between bitline contacts (38) and storage node contact (32) cause large problems during photolithography because dark areas are difficult to achieve when using Levenson Phaseshift. Because Levenson Phaseshift depends on wave cancellations between nearby features, commonly known as destructive interferences, the resultant printability of the pattern is largely a function of the symmetry and separation distances. When non-symmetries in the pattern occur, the result is weaker cancellations of fields (i.e. between features) and a large loss of image contrast and depth of focus during the printing step. The net result are defects, which increase device failure, can be significantly reduced by the geometry modifications disclosed herein.

摘要翻译： 用于制造六边形对称单元（例如，动态随机存取存储单元（100））的装置和方法。 电池可以包括位线触点（38），六边形围绕位线触点（38）的存储节点触点（32），也围绕位线触点（38）的存储节点（36），其中一部分形成字段 效应晶体管栅极。 位线触点（38）和存储节点触点（32）之间的大距离在光刻期间引起很大的问题，因为使用Levenson Phaseshift时很难实现暗区。 因为Levenson Phaseshift取决于附近特征之间的波浪消除，通常被称为破坏性干扰，所以模式的最终可印刷性主要是对称性和分离距离的函数。 当图案中的非对称性发生时，结果是在打印步骤期间，场的更弱的取消（即，特征之间）和图像对比度的大的损失和焦点的深度。 最终结果是通过本文公开的几何修改可以显着地减少增加设备故障的缺陷。

公开(公告)号：US6166408A

公开(公告)日：2000-12-26

申请号：US216251

申请日：1998-12-18

申请人： Akitoshi Nishimura ,  Yasutoshi Okuno ,  Rajesh Khamankar ,  Shane R. Palmer

发明人： Akitoshi Nishimura ,  Yasutoshi Okuno ,  Rajesh Khamankar ,  Shane R. Palmer

IPC分类号： H01L21/8242 ,  H01L27/108

CPC分类号： H01L27/10888 ,  H01L27/10805 ,  Y10S257/905

摘要： An apparatus and method for fabrication a hexagonally symmetric cell, (e.g., a dynamic random access memory cell (100)). The cell can comprise a bitline contact (38), storage node contacts (32) hexagonally surrounding the bitline contact (38), storage nodes (36) also surrounding the bitline contact (38), a wordline (30) portions of which form field effect transistor gates. Large distances between bitline contacts (38) and storage node contacts (32) cause large problems during photolithography because dark areas are difficult to achieve when using Levenson Phaseshift. Because Levenson Phaseshift depends on wave cancellations between nearby features, commonly known as destructive interferences, the resultant printability of the pattern is largely a function of the symmetry and separation distances. When non-symmetries in the pattern occur, the result is weaker cancellations of fields (i.e. between features) and a large loss of image contrast and depth of focus during the printing step. The net result are defects, which increase device failure, can be significantly reduced by the geometry modifications disclosed herein.

摘要翻译： 用于制造六边形对称单元（例如，动态随机存取存储单元（100））的装置和方法。 电池可以包括位线触点（38），六边形围绕位线触点（38）的存储节点触点（32），也围绕位线触点（38）的存储节点（36），其中一部分形成字段 效应晶体管栅极。 位线触点（38）和存储节点触点（32）之间的大距离在光刻期间引起很大的问题，因为当使用Levenson Phaseshift时，很难实现暗区。 因为Levenson Phaseshift取决于附近特征之间的波浪消除，通常被称为破坏性干扰，所以模式的最终可印刷性主要是对称性和分离距离的函数。 当图案中的非对称性发生时，结果是在打印步骤期间，场的更弱的取消（即，特征之间）和图像对比度的大的损失和焦点的深度。 最终结果是通过本文公开的几何修改可以显着地减少增加设备故障的缺陷。

公开(公告)号：US6033953A

公开(公告)日：2000-03-07

申请号：US991132

申请日：1997-12-16

申请人： Katsuhiro Aoki ,  Yukio Fukuda ,  Ken Numata ,  Yasutoshi Okuno ,  Akitoshi Nishimura

发明人： Katsuhiro Aoki ,  Yukio Fukuda ,  Ken Numata ,  Yasutoshi Okuno ,  Akitoshi Nishimura

IPC分类号： H01G4/33 ,  H01L21/02 ,  H01L21/321 ,  H01L21/8242 ,  H01L21/8246 ,  H01L27/10 ,  H01L27/105 ,  H01L27/108

CPC分类号： H01L27/1085 ,  H01L28/60 ,  H01L21/32115

摘要： A dielectric capacitor is provided which has a reduced leakage current. The surface of a first electrode (38) of the capacitor is electropolished and a dielectric film (40) and a second electrode (37) are successively laminated on it. The convex parts pointed end (38a) existing on the surface of the first electrode is very finely polished uniformly by dissolving according to electropolishing, a spherical curved surface in which the radius of curvature has been enlarged is formed, and the surface of the first electrode is flattened. Therefore, concentration of electrolysis can be prevented during the operation at the interface of the first electrode and the dielectric film, and the leakage current can be reduced considerably.

摘要翻译： 提供了具有减小的漏电流的介质电容器。 对电容器的第一电极（38）的表面进行电解抛光，并在其上依次层压电介质膜（40）和第二电极（37）。 存在于第一电极表面上的凸部尖端（38a）通过电解抛光溶解而形成非常细微的抛光，形成曲面半径扩大的球面曲面，第一电极的表面 扁平化 因此，在第一电极和电介质膜的界面的操作期间可以防止电解浓度，并且可以显着降低泄漏电流。

公开(公告)号：US20100219481A1

公开(公告)日：2010-09-02

申请号：US12684803

申请日：2010-01-08

申请人： Joshua Tseng ,  Yasutoshi Okuno ,  Lars-Ake Ragnarsson ,  Tom Schram ,  Stefan Kubicek ,  Thomas Y. Hoffmann ,  Naohisa Sengoku

发明人： Joshua Tseng ,  Yasutoshi Okuno ,  Lars-Ake Ragnarsson ,  Tom Schram ,  Stefan Kubicek ,  Thomas Y. Hoffmann ,  Naohisa Sengoku

IPC分类号： H01L27/092 ,  H01L21/28

摘要： A method for manufacturing a dual work function device is disclosed. In one aspect, the process includes a first and second region in a substrate. The method includes forming a first transistor in the first region which has a first work function. Subsequently, a second transistor is formed in the second region having a different work function. The process of forming the first transistor includes providing a first gate dielectric stack having a first gate dielectric layer and a first gate dielectric capping layer on the first gate dielectric layer, performing a thermal treatment to modify the first gate dielectric stack, the modified first gate dielectric stack defining the first work function, providing a first metal gate electrode layer on the modified first gate dielectric stack, and patterning the first metal gate electrode layer and the modified first gate dielectric stack.

摘要翻译： 公开了一种用于制造双功能功能装置的方法。 在一个方面，该方法包括在基底中的第一和第二区域。 该方法包括在具有第一功能的第一区域中形成第一晶体管。 随后，在具有不同功函数的第二区域中形成第二晶体管。 形成第一晶体管的过程包括提供在第一栅极介电层上具有第一栅极介电层和第一栅极介电覆盖层的第一栅极电介质堆叠，执行热处理以修改第一栅极电介质堆叠，修改的第一栅极 限定第一功函数的电介质叠层，在修改的第一栅极电介质堆叠上提供第一金属栅极电极层，以及对第一金属栅极电极层和修改的第一栅极电介质堆叠进行构图。

公开(公告)号：US20100032733A1

公开(公告)日：2010-02-11

申请号：US12580573

申请日：2009-10-16

申请人： Satoru ITOU ,  Yasutoshi Okuno ,  Takashi Nakabayashi

发明人： Satoru ITOU ,  Yasutoshi Okuno ,  Takashi Nakabayashi

IPC分类号： H01L29/78 ,  H01L21/20

CPC分类号： H01L29/7833 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636

摘要： A semiconductor device includes: a semiconductor substrate having an element formation region containing impurities of a first conductivity type; a gate electrode formed on the element formation region with a gate insulating film interposed therebetween; and a silicon alloy layer formed on a lateral side of the gate electrode in the element formation region, and containing impurities of a second conductivity type. A boundary layer containing impurities of the second conductivity type is formed between the silicon alloy layer and the element formation region.

摘要翻译： 半导体器件包括：具有包含第一导电类型的杂质的元素形成区域的半导体衬底; 形成在元件形成区域上的栅电极，其间插入有栅极绝缘膜; 以及形成在元件形成区域中的栅电极的侧面上并且包含第二导电类型的杂质的硅合金层。 在硅合金层和元件形成区之间形成含有第二导电型杂质的边界层。

公开(公告)号：US07446015B2

公开(公告)日：2008-11-04

申请号：US11006665

申请日：2004-12-08

申请人： Yasutoshi Okuno ,  Masaru Yamada

发明人： Yasutoshi Okuno ,  Masaru Yamada

IPC分类号： H01L21/76

CPC分类号： H01L21/31053 ,  H01L21/76229 ,  H01L27/0207

摘要： A semiconductor device includes a circuit formation region which is formed in a semiconductor substrate and includes a plurality of element formation regions surrounded by isolation regions, respectively. A stress effect relief region of a predetermined width is formed around the circuit formation region to relieve a stress effect of the isolation regions on the operation characteristics of elements formed in the element formation regions and a plurality of dummy features are formed in the stress effect relief region and other part of the circuit formation region than the element formation regions at predetermined distances, the dummy features having the same composition as the element formation regions and predetermined planar dimensions. The predetermined planar dimensions of the dummy features are defined by longitudinal and transverse dimensions most frequently found in the plurality of element formation regions formed in the circuit formation region or selected dimensions of the element formation regions. The predetermined distances between the dummy features are specified as the minimum allowable value in respect of the manufacture of the elements.

摘要翻译： 半导体器件包括电路形成区域，其形成在半导体衬底中并且包括被隔离区包围的多个元件形成区域。 在电路形成区域的周围形成预定宽度的应力作用缓和区域，以减轻隔离区域对形成在元件形成区域中的元件的操作特性的应力作用，并且在应力效应释放中形成多个虚拟特征 区域和电路形成区域的其他部分比元件形成区域预定距离，虚拟特征具有与元件形成区域相同的组成和预定的平面尺寸。 虚拟特征的预定平面尺寸由在电路形成区域中形成的多个元件形成区域或元件形成区域的选定尺寸中最常见的纵向和横向尺寸限定。 虚拟特征之间的预定距离被指定为关于元件的制造的最小允许值。

公开(公告)号：US07253436B2

公开(公告)日：2007-08-07

申请号：US10895833

申请日：2004-07-22

申请人： Michikazu Matsumoto ,  Yasutoshi Okuno ,  Katsuyoshi Joukyu ,  Tetsuya Matsutani

发明人： Michikazu Matsumoto ,  Yasutoshi Okuno ,  Katsuyoshi Joukyu ,  Tetsuya Matsutani

IPC分类号： H01L23/58

CPC分类号： G01R31/2884 ,  G01R31/2853

摘要： A resistance defect assessment device provided on a wafer for assessing a resistance variation defect in a component of an integrated circuit device, the resistance defect assessment device including test patterns capable of measuring a resistance variation component to be the resistance variation defect in each chip area or each shot area of the wafer, wherein the number of test patterns included in one chip area or one shot area is set so that it is possible to estimate the yield of the integrated circuit device.

摘要翻译： 一种电阻缺陷评估装置，设置在用于评估集成电路器件的部件中的电阻变化缺陷的晶片上，所述电阻缺陷评估装置包括能够测量每个芯片区域中的电阻变化分量的电阻变化分量作为电阻变化缺陷的测试图案， 晶片的每个照射区域，其中设置包括在一个芯片区域或一个照射区域中的测试图案的数量，使得可以估计集成电路器件的产量。

公开(公告)号：US07249343B2

公开(公告)日：2007-07-24

申请号：US10891112

申请日：2004-07-15

申请人： Yasutoshi Okuno

发明人： Yasutoshi Okuno

IPC分类号： G06F17/50 ,  G06F19/00 ,  G06K9/00

CPC分类号： H01L22/20

摘要： After a process is performed on a substrate, the in-plane distribution over the substrate is measured. Measured data of the in-plane distribution which is obtained by the measurement is stored. A model formula of the in-plane distribution is calculated from the stored measured data. The measured data is compared with the model formula. A set of parameters of the model formula is calculated, and the calculated parameters are stored as data of the in-plane distribution over the substrate. The measured data includes measurement coordinates over the substrate. The model formula is obtained by modeling the tendency that the in-plane distribution concentrically varies and the tendency that the in-plane distribution varies along a diameter direction.

摘要翻译： 在基板上进行处理之后，测量衬底上的面内分布。 存储通过测量获得的平面内分布的测量数据。 根据存储的测量数据计算面内分布的模型公式。 将测量数据与模型公式进行比较。 计算出模型公式的一组参数，将计算出的参数作为平面分布的数据存储在基板上。 测量数据包括基板上的测量坐标。 模型公式通过模拟面内分布同心变化的趋势和面内分布沿直径方向变化的趋势来获得。

公开(公告)号：US20060189087A1

公开(公告)日：2006-08-24

申请号：US11356959

申请日：2006-02-21

申请人： Yasutoshi Okuno ,  Michikazu Matsumoto

发明人： Yasutoshi Okuno ,  Michikazu Matsumoto

IPC分类号： H01L21/336

CPC分类号： H01L21/28518 ,  H01L21/28052 ,  H01L29/665

摘要： A gate electrode is formed on a silicon substrate, and then source/drain regions are formed at both sides of the gate electrode in the silicon substrate. Thereafter, an alloyed silicide layer is formed on the source/drain regions. The step of forming the alloyed silicide layer includes the step of depositing a first metal film, a nickel film and a second metal film in this order to form a multilayer metal film and the step of performing heat treatment after the formation of the multilayer metal film.

公开(公告)号：US06265262B1

公开(公告)日：2001-07-24

申请号：US09587363

申请日：2000-06-02

申请人： Yasutoshi Okuno ,  Akihiko Tsuzumitani ,  Yoshihiro Mori

发明人： Yasutoshi Okuno ,  Akihiko Tsuzumitani ,  Yoshihiro Mori

IPC分类号： H01L218242

CPC分类号： H01L21/7687 ,  H01L21/28518 ,  H01L21/76849 ,  H01L21/76889 ,  H01L27/10852 ,  H01L28/60

摘要： A silicon film is formed within a contact hole formed in a first insulating film on a semiconductor substrate in a manner that an upper portion of the contact hole remains, and a cobalt film is then deposited on the silicon film. Thereafter, a heat treatment is carried out so as to react the silicon film with the cobalt film, thereby forming a cobalt silicide layer in the surface portion of the silicon film. A barrier layer is formed on the cobalt silicide layer so as to completely fill the contact hole, and thus, a plug including the polysilicon film, the cobalt silicide layer and the barrier layer is formed. After a recess is formed in a second insulating film deposited on the first insulating film so as to expose the top surface of the plug, a capacitor bottom electrode, a capacitor dielectric film and a capacitor top electrode are successively formed in the recess.

摘要翻译： 在半导体基板上形成在第一绝缘膜上的接触孔内形成硅膜，使得保留接触孔的上部，然后在硅膜上沉积钴膜。 此后，进行热处理以使硅膜与钴膜反应，从而在硅膜的表面部分形成钴硅化物层。 在硅化钴层上形成阻挡层，以完全填充接触孔，从而形成包括多晶硅膜，硅化钴层和阻挡层的插塞。 在沉积在第一绝缘膜上的第二绝缘膜中形成凹部以暴露插头的顶面之后，在凹部中依次形成电容器底部电极，电容器电介质膜和电容器顶部电极。