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公开(公告)号：US5862150A
公开(公告)日：1999-01-19
申请号：US963261
申请日：1997-10-28
IPC分类号： G06F3/153 , G06F11/277 , G09G5/00 , G09G5/18 , G09G5/395 , G09G5/397 , G09G5/399 , G06F15/20
CPC分类号： G09G5/395 , G06F11/277
摘要： A method and apparatus for performing signature analysis of video data being output by a RAMDAC so that starting and stopping the sampling of data is made precise so that the data sampled is a known set. The invention uses a timing generator and signature analysis hardware integrated with a RAMDAC to start and stop the sampling and signature calculation of video data on frame boundaries. A signature capture request bit is used to request that the next frame be sampled and a signature calculated. The hardware waits until the beginning of the next frame starts, and then samples data until the frame ends. The calculated signature is made available in a signature analysis result register for reading. The resulting signature is held in the signature analysis result register until cleared or another signature capture request is made.
摘要翻译： 一种用于执行由RAMDAC输出的视频数据的签名分析的方法和装置，使得开始和停止数据采样是精确的，使得采样的数据是已知的集合。 本发明使用与RAMDAC集成的定时发生器和签名分析硬件来启动和停止帧边界上的视频数据的采样和签名计算。 签名捕获请求位用于请求下一帧被采样并计算签名。 硬件等待直到下一帧开始，然后采样数据直到帧结束。 计算的签名在签名分析结果寄存器中可用于阅读。 结果签名保存在签名分析结果寄存器中，直到清除或另一个签名捕获请求。
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公开(公告)号：US5696534A
公开(公告)日：1997-12-09
申请号：US408272
申请日：1995-03-21
CPC分类号： G09G5/395
摘要： A method and for multiplexing pixel data from a frame buffer to a RAMDAC to reduce the number of pins required. For many graphics operations optimal performance is achieved by storing an entire 32-bit pixel in a single RAM chip. When displaying video data from a frame buffer, pixels must be read out serially from the frame buffer at real-time speeds. A frame buffer memory with 16 pins for serial video output is used. An entire 32-bit pixel is stored in a single RAM chip. For a 32-bit pixel containing four byte (8-bit) quantities designated X, B, G and R, on the first clock cycle, the X and B bytes are made available on the 16 pins of the frame buffer. On the next clock cycle, the G and R bytes are made available. Thus, over two cycles the entire 32-bit pixel is output from the frame buffer to a RAMDAC which samples the X and B bytes on 16 input pins. The RAMDAC stores these X and B bytes in an internal register. On the next clock cycle it samples the G and R bytes. The DAC then reassembles the X, B, G and R bytes into a single 32-bit pixel for conversion into video. In this manner, 32-bit pixels are communicated across a 16-bit pixel data bus.
摘要翻译： 一种用于将来自帧缓冲器的像素数据复用到RAMDAC的方法，以减少所需的引脚数。 对于许多图形操作，通过将整个32位像素存储在单个RAM芯片中来实现最佳性能。 当从帧缓冲器显示视频数据时，像素必须以实时速度从帧缓冲器中串行读出。 使用具有16个引脚用于串行视频输出的帧缓冲存储器。 整个32位像素存储在单个RAM芯片中。 对于包含在第一个时钟周期指定为X，B，G和R的四个字节（8位）的32位像素，X和B字节在帧缓冲器的16个引脚上可用。 在下一个时钟周期中，G和R字节可用。 因此，在两个周期内，整个32位像素从帧缓冲器输出到RAMDAC，其对16个输入引脚上的X和B字节进行采样。 RAMDAC将这些X和B字节存储在内部寄存器中。 在下一个时钟周期，它对G和R字节进行采样。 然后，DAC将X，B，G和R字节重新组合成单个32位像素，以转换为视频。 以这种方式，32位像素在16位像素数据总线上传送。
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3.发明授权
公开(公告)号：US5963200A
公开(公告)日：1999-10-05
申请号：US914973
申请日：1997-08-20
IPC分类号： G06F3/153 , G06F3/14 , G09G5/00 , G09G5/06 , G09G5/08 , G09G5/12 , G09G5/18 , G09G5/397 , G09G5/399 , H04N13/00
CPC分类号： G06F3/1446 , G09G5/06 , G09G5/08 , G09G5/12 , G09G5/18 , H04N13/0048 , H04N13/0051 , H04N13/0497 , G06F3/1454 , G09G2310/0224 , G09G2360/04 , H04N13/0055 , H04N13/0429
摘要： A method and apparatus for synchronizing the vertical blanking of multiple frame buffers which may exist on the same computer or separate computers for certain applications including stereo display, virtual reality and video recording, which require such synchronization. To obtain the required synchronization one frame buffer is designation as the master. It provides a signal called FIELD that changes state (0 to 1 or 1 to 0) at the start of every vertical sync event on the master frame buffer. All other frame buffers are set to be slaves. Their timing generators sample the master's FIELD signal. When they detect the master's FIELD signal changing state, they set their own internal timing to match to thereby achieve frame synchronization.
摘要翻译： 用于同步可能存在于同一计算机上的多个帧缓冲器的垂直消隐的方法和装置，或者用于包括需要这种同步的立体显示，虚拟现实和视频记录的某些应用的单独的计算机。 为了获得所需的同步，一帧缓冲器被指定为主机。 它提供一个称为FIELD的信号，它在主帧缓冲区上的每个垂直同步事件的开始处改变状态（0到1或1到0）。 所有其他帧缓冲区都被设置为从站。 他们的定时发生器对主站的FIELD信号进行采样。 当他们检测到主站的FIELD信号改变状态时，它们设置自己的内部时序来匹配，从而实现帧同步。
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公开(公告)号：US06961861B2
公开(公告)日：2005-11-01
申请号：US10085184
申请日：2002-02-27
申请人： Alex N. Koltzoff , David C. Kehlet
发明人： Alex N. Koltzoff , David C. Kehlet
CPC分类号： H04L7/0008
摘要： A interface, which connects memory and an integrated circuit, having a write path and read path that allow synchronous data propagation is provided. Further, a method for synchronizing data propagation through a read path and a write path of an interface is provided. The interface uses clock signals and paths based on a clock signal to synchronize the flow of data through various paths within the interface.
摘要翻译： 提供了一种连接存储器和集成电路的接口，具有允许同步数据传播的写入路径和读取路径。 此外，提供了一种用于使通过读取路径的数据传播和接口的写入路径同步的方法。 该接口使用基于时钟信号的时钟信号和路径来通过接口内的各种路径同步数据流。
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5.发明授权Rasterization using two-dimensional tiles and alternating bins for improved rendering utilization 有权使用二维瓦片和交替箱体进行光栅化，以提高渲染利用率公开(公告)号：US06803916B2
公开(公告)日：2004-10-12
申请号：US09861475
申请日：2001-05-18
申请人： Nandini Ramani , David C. Kehlet , Ewa M. Kubalska , Michael G. Lavelle , Michael A. Wasserman , Kevin Tang , Yan Yan Tang
发明人： Nandini Ramani , David C. Kehlet , Ewa M. Kubalska , Michael G. Lavelle , Michael A. Wasserman , Kevin Tang , Yan Yan Tang
IPC分类号： G06T120
摘要： A system and method for rasterizing and rendering graphics data is disclosed. Vertices may be grouped to form primitives such as triangles, which are rasterized using two-dimensional arrays of samples bins. Individual samples may be selected from the bins according to different criteria such as memory bank allocation to improve utilization of the system's rendering pipeline. Since the arrays may have more bins than the number of evaluation units in the rendering pipeline, the samples from the bins may be stored to FIFO memories to allow invalid or empty samples (those outside the primitive being rendered) to be removed. The samples may then be filtered to form pixels that are displayable to form an image on a display device.
摘要翻译： 公开了一种用于光栅化和渲染图形数据的系统和方法。 顶点可以被分组以形成诸如三角形的图元，其使用样本仓的二维阵列进行光栅化。 可以根据诸如存储体分配的不同标准从箱中选择单个样本，以提高系统的渲染管线的利用率。 由于阵列可以具有比渲染流水线中的评估单元数更多的存储单元，所以来自存储区的样本可以被存储到FIFO存储器中以允许去除无效或空的样本（被渲染的原始图像之外的样本）。 然后可以对样本进行滤波以形成可显示以在显示装置上形成图像的像素。
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公开(公告)号：US07042452B1
公开(公告)日：2006-05-09
申请号：US10677671
申请日：2003-10-02
IPC分类号： G06T15/30
CPC分类号： G06T11/203
摘要： A graphics system invokes a dicing process if one or more edges of a triangle T have length greater than a maximum length (LMAX), invokes a central subdivision process if a coverage estimate for the triangle T is greater than a maximum coverage and all edges of triangle T have length less than or equal to LMAX, invokes rendering of a sequence of one or more single-layer triangles based on triangle T if the coverage estimate for triangle T is less than or equal to the maximum coverage and all edges have length less than or equal to LMAX. Said invocation of rendering of the sequence of single-layer triangles results in the application of a plurality of texture layers to samples corresponding to triangle T. The samples are stored in the TAB between the application of successive layers of said plurality of texture layers.
摘要翻译： 如果三角形T的一个或多个边缘的长度大于最大长度（L MAX MAX），则图形系统调用切割过程，如果三角形T的覆盖率估计值较大则调用中心细分过程 比最大覆盖范围和三角形T的所有边缘的长度小于或等于L MAX MAX，如果三角形的覆盖率估计，则调用基于三角形T的一个或多个单层三角形的序列的渲染 T小于或等于最大覆盖范围，并且所有边缘的长度小于或等于L MAX MAX。 所述对单层三角形序列的再现的调用导致将多个纹理层应用于对应于三角形T的样本。样本在所述多个纹理层的连续层的应用之间存储在TAB中。
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7.发明授权Graphics primitive size estimation and subdivision for use with a texture accumulation buffer 有权用于纹理累积缓冲区的图形原始尺寸估计和细分公开(公告)号：US06914610B2
公开(公告)日：2005-07-05
申请号：US09861192
申请日：2001-05-18
申请人： Michael G. Lavelle , Wayne A. Morse , Rangit S. Oberoi , David C. Kehlet , Michael A. Wasserman , Brian D. Emberling , Roger C. Swanson
发明人： Michael G. Lavelle , Wayne A. Morse , Rangit S. Oberoi , David C. Kehlet , Michael A. Wasserman , Brian D. Emberling , Roger C. Swanson
摘要： A graphics system configured to apply multiple layers of texture information to primitives. The graphics system receives parameters defining a primitive and performs a size test on the primitive. If the size test cannot guarantee that a fragment size of the primitive is less than or equal to a fragment capacity of a texture accumulation buffer, the primitive is divided into subprimitives, and the graphics system applies the multiple layers of texture to fragments which intersect the primitive. The graphics system switches from a current layer to the layer next when it has applied textures corresponding to the current layer to all the fragments intersecting the primitive. The graphics system stores color values associated with the primitive fragments in the texture accumulation buffer between the application of successive texture layers.
摘要翻译： 图形系统被配置为将多层纹理信息应用于原语。 图形系统接收定义原语的参数，并对原语进行大小测试。 如果大小测试不能保证原语的片段大小小于或等于纹理累加缓冲区的片段容量，则将原语划分为子标识符，并且图形系统将多层纹理应用于与 原始。 当图形系统将与当前层对应的纹理应用于与图元相交的所有片段时，图形系统将从当前图层切换到该图层。 图形系统在连续纹理层的应用之间存储与纹理累积缓冲器中的原始片段相关联的颜色值。
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8.发明授权Graphics data synchronization with multiple data paths in a graphics accelerator 有权图形数据同步与图形加速器中的多个数据路径公开(公告)号：US06864892B2
公开(公告)日：2005-03-08
申请号：US10093835
申请日：2002-03-08
CPC分类号： G09G5/36 , G06T15/005
摘要： A system and method for preserving the order of data items through a divergence-and-reconvergence of two or more paths in a hardware device. A host processor may write a first token to a first path in the hardware device. A convergence unit in the hardware device may receive and store the first token in a synchronization register. The host processor may poll the synchronization register to determine when the first token arrives in the synchronization register. In response to determining that the first token has arrived in the synchronization register, the host processor may safely write a sequence of one or more data items to a second path in the hardware device.
摘要翻译： 一种用于通过硬件设备中两个或多个路径的发散和再聚合来保持数据项的顺序的系统和方法。 主处理器可以将第一令牌写入硬件设备中的第一路径。 硬件设备中的会聚单元可以将第一令牌接收并存储在同步寄存器中。 主处理器可以轮询同步寄存器以确定第一个令牌何时到达同步寄存器。 响应于确定第一令牌已经到达同步寄存器，主处理器可以安全地将一个或多个数据项的序列写入硬件设备中的第二路径。
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公开(公告)号：US06833834B2
公开(公告)日：2004-12-21
申请号：US10021096
申请日：2001-12-12
IPC分类号： G06F1300
CPC分类号： G09G3/006 , G06F3/1431 , G09G5/001 , G09G5/18 , G09G5/363 , G09G5/395 , G09G2360/123
摘要： A graphics system includes a frame buffer, a write address generator, and a pixel buffer. A burst of pixels received from the frame buffer may not be in display order. In one embodiment, a write address generator calculates a write address for each pixel in the burst of pixels output from the frame buffer. The write address corresponds to a relative display order within the burst for each respective pixel. Each pixel in the burst is stored to its write address in the pixel buffer. This way, the pixels in the burst are stored in display order within the pixel buffer.
摘要翻译： 图形系统包括帧缓冲器，写地址生成器和像素缓冲器。 从帧缓冲器接收到的像素突发可能不是显示顺序。 在一个实施例中，写地址生成器计算从帧缓冲器输出的像素突发中的每个像素的写入地址。 写入地址对应于每个相应像素的突发内的相对显示顺序。 突发中的每个像素被存储到像素缓冲器中的其写入地址。 这样，突发中的像素以像素缓冲器内的显示顺序存储。
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10.发明授权Over-evaluating samples during rasterization for improved datapath utilization 有权在光栅化期间对样本进行过度评估，以提高数据路径利用率公开(公告)号：US06924820B2
公开(公告)日：2005-08-02
申请号：US09962995
申请日：2001-09-25
申请人： Nandini Ramani , David C. Kehlet , Michael G. Lavelle , Mark E. Pascual , Ewa M. Kubalska , Yi-Ming Tian
发明人： Nandini Ramani , David C. Kehlet , Michael G. Lavelle , Mark E. Pascual , Ewa M. Kubalska , Yi-Ming Tian
CPC分类号： G06T11/40
摘要： A system and method for rasterizing and rendering graphics data is disclosed. Vertices may be grouped to form primitives such as triangles, which are rasterized using two-dimensional arrays of samples bins. To overcome fragmentation problems, the system's sample evaluation hardware may be configured to over-evaluate samples each clock cycle. Since a number of the samples will typically not survive evaluation because they will be outside the primitive being rendered, the remaining surviving samples may be combined into sets, with one set being forwarded to subsequent pipeline stages each clock cycle in order to attempt to keep the pipeline utilization high.
摘要翻译： 公开了一种用于光栅化和渲染图形数据的系统和方法。 顶点可以被分组以形成诸如三角形的图元，其使用样本仓的二维阵列进行光栅化。 为了克服分裂问题，系统的样本评估硬件可能被配置为对每个时钟周期的样本进行过度评估。 由于许多样本通常不能存活，因为它们将不在渲染原始图像之外，剩余的存活样本可以组合成集合，其中一个集合被转发到每个时钟周期的后续流水线阶段，以便尝试保持 管道利用率高。
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