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    Solid state optical imaging pixel with resistive load
    1.
    发明授权
    Solid state optical imaging pixel with resistive load 失效
    具有电阻负载的固态光学成像像素

    公开(公告)号：US06188056B1

    公开(公告)日：2001-02-13

    申请号：US09103753

    申请日：1998-06-24

    申请人： Alexander Kalnitsky ,  Frank Randolph Bryant ,  Marco Sabatini

    发明人： Alexander Kalnitsky ,  Frank Randolph Bryant ,  Marco Sabatini

    IPC分类号： H01L2700

    CPC分类号： H01L27/14665 ,  H01L27/14609 ,  H01L31/0352

    摘要： Disclosed is a CMOS image sensor that includes pixels employing a radiation-sensitive resistive element in which the resistance of the element changes in response to the quantity of radiation striking it. The resistive elements are made from an appropriately doped polycrystalline semiconductor material such as polysilicon. The pixels are provided on a semiconductor device in which the photosensitive resistive elements are provided on a first layer and the pixel associated transistors are provided on a second layer. The fill factor may be approach 100 percent for such pixels.

    摘要翻译： 公开了一种CMOS图像传感器，其包括采用辐射敏感电阻元件的像素，其中元件的电阻响应于其的辐射量而变化。 电阻元件由诸如多晶硅的适当掺杂的多晶半导体材料制成。 像素设置在半导体器件上，其中光敏电阻元件设置在第一层上，像素相关联的晶体管设置在第二层上。 这种像素的填充因子可能接近100％。

    Photodiode structure augmented with active area photosensitive regions
    2.
    发明授权
    Photodiode structure augmented with active area photosensitive regions 失效
    光电二极管结构增加了有源区光敏区

    公开(公告)号：US5982011A

    公开(公告)日：1999-11-09

    申请号：US977468

    申请日：1997-11-24

    申请人： Alexander Kalnitsky ,  Marco Sabatini

    发明人： Alexander Kalnitsky ,  Marco Sabatini

    IPC分类号： H01L27/144 ,  H01L27/14

    CPC分类号： H01L27/144

    摘要： A photodiode structure augmented with active area photosensitive regions is used for detecting impinging radiation. The photodiode includes a semiconductor base layer doped with impurities of a first carrier type, a field oxide layer disposed upon the base layer with an opening formed therethrough, a plurality of auxiliary oxide layers wherein each is separately disposed upon the base layer, and a semiconductor diffusion layer doped with impurities of a second carrier type arranged upon the base layer and in contact with the oxide layers. When the photodiode is electrically energized, a plurality of integral photosensitive regions is created within the depletion region to facilitate the detection of impinging radiation at an increased quantum efficiency.

    摘要翻译： 增加了有源区光敏区域的光电二极管结构用于检测入射辐射。 光电二极管包括掺杂有第一载流子类型的杂质的半导体基底层，设置在其上形成有开口的基底层上的场氧化物层，其中分别设置在基底层上的多个辅助氧化物层，以及半导体 扩散层，掺杂有布置在基底层上并与氧化物层接触的第二载体类型的杂质。 当光电二极管被通电时，在耗尽区内产生多个整体感光区域，以便以增加的量子效率检测入射辐射。

    CMOS compatible BioFET
    5.
    发明授权
    CMOS compatible BioFET 有权
    CMOS兼容的BioFET

    公开(公告)号：US09459234B2

    公开(公告)日：2016-10-04

    申请号：US13480161

    申请日：2012-05-24

    申请人： Alexander Kalnitsky ,  Yi-Shao Liu ,  Kai-Chih Liang ,  Chia-Hua Chu ,  Chun-Ren Cheng ,  Chun-Wen Cheng

    发明人： Alexander Kalnitsky ,  Yi-Shao Liu ,  Kai-Chih Liang ,  Chia-Hua Chu ,  Chun-Ren Cheng ,  Chun-Wen Cheng

    IPC分类号： H01L51/05 ,  G01N27/414 ,  H01L51/00

    CPC分类号： G01N27/4145 ,  G01N27/414 ,  G01N27/4148 ,  H01L21/84 ,  H01L27/1203 ,  H01L51/0093

    摘要： The present disclosure provides a bio-field effect transistor (BioFET) and a method of fabricating a BioFET device. The method includes forming a BioFET using one or more process steps compatible with or typical to a complementary metal-oxide-semiconductor (CMOS) process. The BioFET device may include a substrate; a gate structure disposed on a first surface of the substrate and an interface layer formed on the second surface of the substrate. The interface layer may allow for a receptor to be placed on the interface layer to detect the presence of a biomolecule or bio-entity.

    摘要翻译： 本公开提供了生物场效应晶体管（BioFET）和制造BioFET器件的方法。 该方法包括使用与互补金属氧化物半导体（CMOS）工艺兼容或典型的一个或多个工艺步骤形成BioFET。 BioFET器件可以包括衬底; 设置在基板的第一表面上的栅极结构和形成在基板的第二表面上的界面层。 界面层可以允许将受体置于界面层上以检测生物分子或生物实体的存在。

    Method of manufacturing a junction barrier Schottky diode with dual silicides
    7.
    发明授权
    Method of manufacturing a junction barrier Schottky diode with dual silicides 有权
    制造具有双重硅化物的结屏障肖特基二极管的方法

    公开(公告)号：US08101511B2

    公开(公告)日：2012-01-24

    申请号：US12774762

    申请日：2010-05-06

    申请人： Dev Alok Girdhar ,  Michael David Church ,  Alexander Kalnitsky

    发明人： Dev Alok Girdhar ,  Michael David Church ,  Alexander Kalnitsky

    IPC分类号： H01L21/28 ,  H01L21/44

    CPC分类号： H01L29/872 ,  H01L27/0629 ,  H01L29/456 ,  H01L29/47 ,  H01L29/7833

    摘要： An integrated circuit, including a junction barrier Schottky diode, has an N type well, a P-type anode region in the surface of the well, and an N-type Schottky region in the surface of the well and horizontally abutting the anode region. A first silicide layer is on and makes a Schottky contact to the Schottky region and is on an adjoining anode region. A second silicide layer of a different material than the first silicide is on the anode region. An ohmic contact is made to the second silicide on the anode region and to the well.

    摘要翻译： 包括结势垒肖特基二极管的集成电路具有N型阱，阱表面中的P型阳极区域和阱表面中的N型肖特基区域，并且水平地邻接阳极区域。 第一硅化物层在肖特基区域上并与其相邻的阳极区域形成肖特基接触。 与第一硅化物不同的第二硅化物层位于阳极区上。 对阳极区域和阱的第二硅化物进行欧姆接触。

    MULTIPLE TIME PROGRAMMABLE (MTP) PMOS FLOATING GATE-BASED NON-VOLATILE MEMORY DEVICE FOR A GENERAL PURPOSE CMOS TECHNOLOGY WITH THICK GATE OXIDE
    8.
    发明申请
    MULTIPLE TIME PROGRAMMABLE (MTP) PMOS FLOATING GATE-BASED NON-VOLATILE MEMORY DEVICE FOR A GENERAL PURPOSE CMOS TECHNOLOGY WITH THICK GATE OXIDE 有权
    多通道时间可编程（MTP）PMOS浮动栅基非易失性存储器件用于一般用途CMOS技术与厚栅氧化物

    公开(公告)号：US20110176368A1

    公开(公告)日：2011-07-21

    申请号：US13077065

    申请日：2011-03-31

    申请人： Alexander Kalnitsky ,  Michael Church

    发明人： Alexander Kalnitsky ,  Michael Church

    IPC分类号： G11C16/04 ,  H01L29/94

    CPC分类号： G11C16/0433 ,  G11C16/10 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11558

    摘要： A multiple time programmable (MTP) memory cell, in accordance with an embodiment, includes a floating gate PMOS transistor, a high voltage NMOS transistor, and an n-well capacitor. The floating gate PMOS transistor includes a source that forms a first terminal of the memory cell, a drain and a gate. The high voltage NMOS transistor includes a source connected to ground, an extended drain connected to the drain of the PMOS transistor, and a gate forming a second terminal of the memory cell. The n-well capacitor includes a first terminal connected to the gate of the PMOS transistor, and a second terminal forming a third terminal of the memory cell. The floating gate PMOS transistor can store a logic state. Combinations of voltages can be applied to the first, second and third terminals of the memory cell to program, inhibit program, read and erase the logic state.

    摘要翻译： 根据实施例的多时间可编程（MTP）存储单元包括浮置栅极PMOS晶体管，高电压NMOS晶体管和n阱电容器。 浮置栅极PMOS晶体管包括形成存储单元的第一端子，漏极和栅极的源极。 高电压NMOS晶体管包括连接到地的源极，连接到PMOS晶体管的漏极的扩展漏极和形成存储器单元的第二端子的栅极。 n阱电容器包括连接到PMOS晶体管的栅极的第一端子和形成存储器单元的第三端子的第二端子。 浮置栅极PMOS晶体管可以存储逻辑状态。 可以将组合的电压施加到存储单元的第一，第二和第三端子，以编程，禁止程序，读取和擦除逻辑状态。

    Memory array of floating gate-based non-volatile memory cells
    9.
    发明授权
    Memory array of floating gate-based non-volatile memory cells 有权
    基于浮动栅极的非易失性存储单元的存储器阵列

    公开(公告)号：US07903465B2

    公开(公告)日：2011-03-08

    申请号：US11861111

    申请日：2007-09-25

    申请人： Hosam Haggag ,  Alexander Kalnitsky ,  Edgardo Laber ,  Michael D. Church ,  Yun Yue

    发明人： Hosam Haggag ,  Alexander Kalnitsky ,  Edgardo Laber ,  Michael D. Church ,  Yun Yue

    IPC分类号： G11C16/06 ,  G11C16/10 ,  G11C16/12

    CPC分类号： G11C16/0433

    摘要： A memory array comprises a plurality of memory cells organized in a matrix of rows and columns. Each of the memory cells includes a high voltage access transistor, a floating gate memory transistor electrically connected to the access transistor, and a coupling capacitor electrically connected to the memory transistor. A first set of word lines are each electrically connected to the capacitor in each of the memory cells in a respective row. A second set of word lines are each electrically connected to the access transistor in each of the memory cells in a respective row. A first set of bit lines are each electrically connected to the access transistor in each of the memory cells in a respective column. A second set of bit lines are each electrically connected to the memory transistor in each of the memory cells in a respective column. Various combinations of voltages can be applied to the word lines and bit lines in operations to program, erase, read, or inhibit a logic state stored by the memory transistor in one or more of the memory cells.

    摘要翻译： 存储器阵列包括以行和列的矩阵组织的多个存储器单元。 每个存储单元包括高电压存取晶体管，电连接到存取晶体管的浮动栅极存储晶体管和电连接到存储晶体管的耦合电容器。 第一组字线分别电连接到相应行中的每个存储器单元中的电容器。 第二组字线各自电连接到相应行中的每个存储单元中的存取晶体管。 第一组位线分别电连接到相应列中每个存储单元中的存取晶体管。 第二组位线分别电连接到相应列中每个存储器单元中的存储晶体管。 在操作中可以对字线和位线施加电压的各种组合，以对存储器晶体管存储在一个或多个存储器单元中的逻辑状态进行编程，擦除，读取或禁止。

    Electrostatic discharge protection of a capacitive type fingerprint sensing array
    10.
    发明授权
    Electrostatic discharge protection of a capacitive type fingerprint sensing array 有权
    电容型指纹感测阵列的静电放电保护

    公开(公告)号：US07768273B1

    公开(公告)日：2010-08-03

    申请号：US12396102

    申请日：2009-03-02

    申请人： Alexander Kalnitsky ,  Alan Kramer

    发明人： Alexander Kalnitsky ,  Alan Kramer

    IPC分类号： G01R27/26

    CPC分类号： H01L27/0248 ,  G06K9/00053

    摘要： A planar fingerprint pattern detecting array includes a large number of individual skin-distance sensing cells that are arranged in a row/column configuration. Each sensing cell includes a first capacitor plate placed vertically under the upper surface of a dielectric layer and a second capacitor plate that is placed vertically under the upper surface of the dielectric layer in close horizontal spatial relation to the first capacitor plate. Electrostatic discharge protection relative to electrostatic potential that may be carried by an ungrounded fingertip is provided by placing a number of grounded metal paths within the dielectric layer to spatially surround each of the first and second capacitor plates, this being done in a manner that does not disturb the ungrounded state of the fingertip.

    摘要翻译： 平面指纹图案检测阵列包括以行/列配置布置的大量单独的皮肤距离感测单元。 每个感测单元包括垂直于电介质层的上表面放置的第一电容器板和垂直于电介质层的上表面放置在与第一电容器板紧密的水平空间关系的第二电容器板。 通过在电介质层内放置多个接地的金属路径以空间地围绕第一和第二电容器板的每一个来提供相对于静电电位的静电放电保护，这是通过不接地的指尖承载的，这是以不是 打扰指尖的未接地状态。