公开(公告)号：US06713381B2

公开(公告)日：2004-03-30

申请号：US10051262

申请日：2002-01-18

申请人： Alexander L. Barr ,  Suresh Venkatesan ,  David B. Clegg ,  Rebecca G. Cole ,  Olubunmi Adetutu ,  Stuart E. Greer ,  Brian G. Anthony ,  Ramnath Venkatraman ,  Gregor Braeckelmann ,  Douglas M. Reber ,  Stephen R. Crown

发明人： Alexander L. Barr ,  Suresh Venkatesan ,  David B. Clegg ,  Rebecca G. Cole ,  Olubunmi Adetutu ,  Stuart E. Greer ,  Brian G. Anthony ,  Ramnath Venkatraman ,  Gregor Braeckelmann ,  Douglas M. Reber ,  Stephen R. Crown

IPC分类号： H01L214763

CPC分类号： H01L21/76849 ,  H01L21/76801 ,  H01L21/76807 ,  H01L21/76813 ,  H01L21/76843 ,  H01L21/76877 ,  H01L23/53233 ,  H01L23/53238 ,  H01L24/11 ,  H01L24/13 ,  H01L2223/54473 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05024 ,  H01L2224/05025 ,  H01L2224/05027 ,  H01L2224/0508 ,  H01L2224/05147 ,  H01L2224/05157 ,  H01L2224/05166 ,  H01L2224/05172 ,  H01L2224/0518 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05186 ,  H01L2224/05572 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2924/0001 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01016 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01044 ,  H01L2924/01046 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01076 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/12042 ,  H01L2924/19041 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05169 ,  H01L2924/013 ,  H01L2924/0496 ,  H01L2924/0539 ,  H01L2924/0538 ,  H01L2924/0537

摘要： An interconnect overlies a semiconductor device substrate (10). In one embodiment, a conductive barrier layer overlies a portion of the interconnect, a passivation layer (92) overlies the conductive barrier layer and the passivation layer (92) has an opening that exposes portions of the conductive barrier layer (82). In an alternate embodiment a passivation layer (22) overlies the interconnect, the passivation layer (22) has an opening (24) that exposes the interconnect and a conductive barrier layer (32) overlies the interconnect within the opening (24).

摘要翻译： 互连覆盖半导体器件衬底（10）。 在一个实施例中，导电阻挡层覆盖在互连的一部分上，钝化层（92）覆盖在导电阻挡层上，钝化层（92）具有暴露导电阻挡层（82）的部分的开口。 在替代实施例中，钝化层（22）覆盖互连，钝化层（22）具有暴露互连的开口（24），并且导电阻挡层（32）覆盖开口（24）内的互连。

公开(公告)号：US06597234B2

公开(公告)日：2003-07-22

申请号：US10017429

申请日：2001-12-14

申请人： Douglas M. Reber ,  Stephen R. Crown

发明人： Douglas M. Reber ,  Stephen R. Crown

IPC分类号： H01H3776

CPC分类号： H01L23/5252 ,  G11C17/18 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： An anti-fuse useful in implementing redundancy in a memory utilizes a normal transistor characteristic that is generally considered undesirable in order to provide two easily detected states. The un-programmed state, which is the high impedance state, is achieved simply with a normal transistor in its non-conductive state. The programmed state, which is the low impedance state, is achieved by forcing a normal transistor to conduct current through its gate. This causes the gate dielectric to become permanently conductive. This programmed transistor then is conductive between its source and drain that is easily differentiated from the transistor that is held in its non-conductive state. The result is a fuse technology using an anti-fuse that provides for easily distinguishable programmed and un-programmed states achieved by electrical programming rather than by laser programming.

摘要翻译： 用于实现存储器中冗余的反熔丝利用通常被认为是不期望的以提供两个容易检测状态的正常晶体管特性。 非编程状态，即高阻抗状态，简单地用非导通状态的正常晶体管实现。 通过强制正常晶体管将电流传导通过其栅极来实现低阻状态的编程状态。 这导致栅极电介质变得永久导电。 然后，该编程晶体管在其源极和漏极之间是导电的，其容易与保持在其非导通状态的晶体管区分开。 结果是采用了一种使用反熔丝的保险丝技术，可以通过电气编程而不是通过激光编程实现轻松区分编程和非编程状态。