公开(公告)号：US20150228603A1

公开(公告)日：2015-08-13

申请号：US14684103

申请日：2015-04-10

申请人： Micron Technology, Inc.

发明人： Jaspreet S. Gandhi

IPC分类号： H01L23/00

CPC分类号： H01L24/14 ,  H01L21/6835 ,  H01L21/7684 ,  H01L21/76898 ,  H01L23/3171 ,  H01L23/3192 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/03462 ,  H01L2224/0347 ,  H01L2224/0361 ,  H01L2224/03825 ,  H01L2224/0384 ,  H01L2224/03845 ,  H01L2224/03914 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/05016 ,  H01L2224/05018 ,  H01L2224/05019 ,  H01L2224/05022 ,  H01L2224/05023 ,  H01L2224/05025 ,  H01L2224/0508 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05555 ,  H01L2224/05556 ,  H01L2224/05564 ,  H01L2224/05568 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/11622 ,  H01L2224/1182 ,  H01L2224/1184 ,  H01L2224/13023 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2924/00014 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01044 ,  H01L2924/01046 ,  H01L2924/05042 ,  H01L2924/0538 ,  H01L2924/05442 ,  H01L2924/07025 ,  H01L2924/10253 ,  H01L2924/01029 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2224/05552

摘要： Some embodiments include a planarization method. A liner is formed across a semiconductor substrate and along posts that extending upwardly from the substrate. Organic fill material is formed over the liner and between the posts. A planarized surface is formed which extends across the posts and across one or both of the liner and the fill material. Some embodiments include a semiconductor construction containing a semiconductor die. Electrically conductive posts extend through the die. The posts have upper surfaces above a backside surface of the die, and have sidewall surfaces extending between the backside surface and the upper surfaces. A liner is across the backside surface of the die and along the sidewall surfaces of the posts. Electrically conductive caps are over the upper surfaces of the posts, and have rims along the liner adjacent the sidewall surfaces of the posts.

摘要翻译： 一些实施例包括平面化方法。 衬套跨越半导体衬底并沿着从衬底向上延伸的柱形成。 有机填充材料形成在衬里上和柱之间。 形成平面化的表面，该平面化表面延伸穿过柱并穿过衬套和填充材料中的一个或两个。 一些实施例包括包含半导体管芯的半导体结构。 导电柱延伸穿过模具。 柱具有在模具的背面上方的上表面，并且具有在背面和上表面之间延伸的侧壁表面。 衬套穿过模具的后表面并且沿着柱的侧壁表面。 导电盖在柱的上表面之上，并且沿着邻近柱的侧壁表面的衬垫具有边缘。

公开(公告)号：US06713381B2

公开(公告)日：2004-03-30

申请号：US10051262

申请日：2002-01-18

申请人： Alexander L. Barr ,  Suresh Venkatesan ,  David B. Clegg ,  Rebecca G. Cole ,  Olubunmi Adetutu ,  Stuart E. Greer ,  Brian G. Anthony ,  Ramnath Venkatraman ,  Gregor Braeckelmann ,  Douglas M. Reber ,  Stephen R. Crown

发明人： Alexander L. Barr ,  Suresh Venkatesan ,  David B. Clegg ,  Rebecca G. Cole ,  Olubunmi Adetutu ,  Stuart E. Greer ,  Brian G. Anthony ,  Ramnath Venkatraman ,  Gregor Braeckelmann ,  Douglas M. Reber ,  Stephen R. Crown

IPC分类号： H01L214763

CPC分类号： H01L21/76849 ,  H01L21/76801 ,  H01L21/76807 ,  H01L21/76813 ,  H01L21/76843 ,  H01L21/76877 ,  H01L23/53233 ,  H01L23/53238 ,  H01L24/11 ,  H01L24/13 ,  H01L2223/54473 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05024 ,  H01L2224/05025 ,  H01L2224/05027 ,  H01L2224/0508 ,  H01L2224/05147 ,  H01L2224/05157 ,  H01L2224/05166 ,  H01L2224/05172 ,  H01L2224/0518 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05186 ,  H01L2224/05572 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2924/0001 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01016 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01044 ,  H01L2924/01046 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01076 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/12042 ,  H01L2924/19041 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05169 ,  H01L2924/013 ,  H01L2924/0496 ,  H01L2924/0539 ,  H01L2924/0538 ,  H01L2924/0537

摘要： An interconnect overlies a semiconductor device substrate (10). In one embodiment, a conductive barrier layer overlies a portion of the interconnect, a passivation layer (92) overlies the conductive barrier layer and the passivation layer (92) has an opening that exposes portions of the conductive barrier layer (82). In an alternate embodiment a passivation layer (22) overlies the interconnect, the passivation layer (22) has an opening (24) that exposes the interconnect and a conductive barrier layer (32) overlies the interconnect within the opening (24).

摘要翻译： 互连覆盖半导体器件衬底（10）。 在一个实施例中，导电阻挡层覆盖在互连的一部分上，钝化层（92）覆盖在导电阻挡层上，钝化层（92）具有暴露导电阻挡层（82）的部分的开口。 在替代实施例中，钝化层（22）覆盖互连，钝化层（22）具有暴露互连的开口（24），并且导电阻挡层（32）覆盖开口（24）内的互连。

公开(公告)号：US20130234319A1

公开(公告)日：2013-09-12

申请号：US13418113

申请日：2012-03-12

申请人： Jaspreet S. Gandhi

发明人： Jaspreet S. Gandhi

IPC分类号： H01L23/498 ,  H01L21/768

CPC分类号： H01L24/14 ,  H01L21/6835 ,  H01L21/7684 ,  H01L21/76898 ,  H01L23/3171 ,  H01L23/3192 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/03462 ,  H01L2224/0347 ,  H01L2224/0361 ,  H01L2224/03825 ,  H01L2224/0384 ,  H01L2224/03845 ,  H01L2224/03914 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/05016 ,  H01L2224/05018 ,  H01L2224/05019 ,  H01L2224/05022 ,  H01L2224/05023 ,  H01L2224/05025 ,  H01L2224/0508 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05555 ,  H01L2224/05556 ,  H01L2224/05564 ,  H01L2224/05568 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/11622 ,  H01L2224/1182 ,  H01L2224/1184 ,  H01L2224/13023 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2924/00014 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01044 ,  H01L2924/01046 ,  H01L2924/05042 ,  H01L2924/0538 ,  H01L2924/05442 ,  H01L2924/07025 ,  H01L2924/10253 ,  H01L2924/01029 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2224/05552

摘要： Some embodiments include a planarization method. A liner is formed across a semiconductor substrate and along posts that extending upwardly from the substrate. Organic fill material is formed over the liner and between the posts. A planarized surface is formed which extends across the posts and across one or both of the liner and the fill material. Some embodiments include a semiconductor construction containing a semiconductor die. Electrically conductive posts extend through the die. The posts have upper surfaces above a backside surface of the die, and have sidewall surfaces extending between the backside surface and the upper surfaces. A liner is across the backside surface of the die and along the sidewall surfaces of the posts. Electrically conductive caps are over the upper surfaces of the posts, and have rims along the liner adjacent the sidewall surfaces of the posts.

摘要翻译： 一些实施例包括平面化方法。 衬套跨越半导体衬底并沿着从衬底向上延伸的柱形成。 有机填充材料形成在衬里上和柱之间。 形成平面化的表面，该平面化表面延伸穿过柱并穿过衬套和填充材料中的一个或两个。 一些实施例包括包含半导体管芯的半导体结构。 导电柱延伸穿过模具。 柱具有在模具的背面上方的上表面，并且具有在背面和上表面之间延伸的侧壁表面。 衬套穿过模具的后表面并且沿着柱的侧壁表面。 导电盖在柱的上表面之上，并且沿着邻近柱的侧壁表面的衬垫具有边缘。

公开(公告)号：US08519516B1

公开(公告)日：2013-08-27

申请号：US13418113

申请日：2012-03-12

申请人： Jaspreet S. Gandhi

发明人： Jaspreet S. Gandhi

IPC分类号： H01L23/498 ,  H01L21/768

CPC分类号： H01L24/14 ,  H01L21/6835 ,  H01L21/7684 ,  H01L21/76898 ,  H01L23/3171 ,  H01L23/3192 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/03462 ,  H01L2224/0347 ,  H01L2224/0361 ,  H01L2224/03825 ,  H01L2224/0384 ,  H01L2224/03845 ,  H01L2224/03914 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/05016 ,  H01L2224/05018 ,  H01L2224/05019 ,  H01L2224/05022 ,  H01L2224/05023 ,  H01L2224/05025 ,  H01L2224/0508 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05555 ,  H01L2224/05556 ,  H01L2224/05564 ,  H01L2224/05568 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/11622 ,  H01L2224/1182 ,  H01L2224/1184 ,  H01L2224/13023 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2924/00014 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01044 ,  H01L2924/01046 ,  H01L2924/05042 ,  H01L2924/0538 ,  H01L2924/05442 ,  H01L2924/07025 ,  H01L2924/10253 ,  H01L2924/01029 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2224/05552

摘要： Some embodiments include a planarization method. A liner is formed across a semiconductor substrate and along posts that extending upwardly from the substrate. Organic fill material is formed over the liner and between the posts. A planarized surface is formed which extends across the posts and across one or both of the liner and the fill material. Some embodiments include a semiconductor construction containing a semiconductor die. Electrically conductive posts extend through the die. The posts have upper surfaces above a backside surface of the die, and have sidewall surfaces extending between the backside surface and the upper surfaces. A liner is across the backside surface of the die and along the sidewall surfaces of the posts. Electrically conductive caps are over the upper surfaces of the posts, and have rims along the liner adjacent the sidewall surfaces of the posts.

摘要翻译： 一些实施例包括平面化方法。 衬套跨越半导体衬底并沿着从衬底向上延伸的柱形成。 有机填充材料形成在衬里上和柱之间。 形成平面化的表面，该平面化表面延伸穿过柱并穿过衬套和填充材料中的一个或两个。 一些实施例包括包含半导体管芯的半导体结构。 导电柱延伸穿过模具。 柱具有在模具的背面上方的上表面，并且具有在背面和上表面之间延伸的侧壁表面。 衬套穿过模具的后表面并且沿着柱的侧壁表面。 导电盖在柱的上表面之上，并且沿着邻近柱的侧壁表面的衬垫具有边缘。

公开(公告)号：US20180108626A1

公开(公告)日：2018-04-19

申请号：US15642742

申请日：2017-07-06

申请人： International Business Machines Corporation

发明人： Ekta Misra ,  Krishna R. Tunga

IPC分类号： H01L23/00

CPC分类号： H01L24/05 ,  H01L24/03 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/02126 ,  H01L2224/0215 ,  H01L2224/02166 ,  H01L2224/02185 ,  H01L2224/0219 ,  H01L2224/03013 ,  H01L2224/0401 ,  H01L2224/05073 ,  H01L2224/05082 ,  H01L2224/05083 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05191 ,  H01L2224/05611 ,  H01L2224/05616 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05657 ,  H01L2224/05666 ,  H01L2224/05669 ,  H01L2224/0567 ,  H01L2224/05676 ,  H01L2224/05681 ,  H01L2224/05684 ,  H01L2224/05687 ,  H01L2224/05691 ,  H01L2224/05693 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2924/07025 ,  H01L2924/3511 ,  H01L2924/35121 ,  H01L2924/014 ,  H01L2924/01047 ,  H01L2924/00014 ,  H01L2924/04953 ,  H01L2924/04941 ,  H01L2924/0455 ,  H01L2924/01073 ,  H01L2924/04541 ,  H01L2924/0469 ,  H01L2924/0463 ,  H01L2924/01013 ,  H01L2924/0476 ,  H01L2924/01074 ,  H01L2924/0496 ,  H01L2924/0538 ,  H01L2924/01044 ,  H01L2924/0479 ,  H01L2924/01027 ,  H01L2924/048 ,  H01L2924/01028 ,  H01L2924/01006

摘要： Embodiments are directed to a method of forming a semiconductor chip package and resulting structures having an annular PSPI region formed under a BLM pad. An annular region is formed under a barrier layer metallurgy (BLM) pad. The annular region includes a photosensitive polyimide (PSPI). A conductive pedestal is formed on a surface of the BLM pad and a solder bump is formed on a surface of the conductive pedestal. The annular PSPI region reduces wafer warpage and ULK peeling stress.

公开(公告)号：US20160160102A1

公开(公告)日：2016-06-09

申请号：US14904145

申请日：2013-07-16

申请人： HITACHI CHEMICAL COMPANY, LTD.

发明人： Tomonori MINEGISHI ,  Kazuyuki MITSUKURA

IPC分类号： C09J179/08 ,  G03F7/038 ,  H01L23/00 ,  C09J7/02

CPC分类号： C09J179/08 ,  C09J7/20 ,  C09J2201/122 ,  C09J2203/326 ,  C09J2205/31 ,  C09J2479/08 ,  G03F7/027 ,  G03F7/037 ,  G03F7/038 ,  G03F7/0387 ,  G03F7/0751 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L2224/1132 ,  H01L2224/1141 ,  H01L2224/1148 ,  H01L2224/131 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/13169 ,  H01L2224/13187 ,  H01L2224/1329 ,  H01L2224/13339 ,  H01L2224/13344 ,  H01L2224/13347 ,  H01L2224/13355 ,  H01L2224/13364 ,  H01L2224/13369 ,  H01L2224/13387 ,  H01L2224/1339 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/27003 ,  H01L2224/271 ,  H01L2224/27436 ,  H01L2224/27515 ,  H01L2224/27618 ,  H01L2224/27848 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/29339 ,  H01L2224/29344 ,  H01L2224/29347 ,  H01L2224/29355 ,  H01L2224/29387 ,  H01L2224/2939 ,  H01L2224/29391 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73104 ,  H01L2224/81002 ,  H01L2224/81203 ,  H01L2224/83002 ,  H01L2224/83203 ,  H01L2224/83855 ,  H01L2224/83856 ,  H01L2224/83862 ,  H01L2224/92 ,  H01L2224/9211 ,  H01L2224/94 ,  H01L2924/07025 ,  H01L2924/066 ,  H01L2924/0665 ,  H01L2924/00014 ,  H01L2924/05442 ,  H01L2924/00012 ,  H01L2224/27 ,  H01L2224/11 ,  H01L2924/014 ,  H01L2924/0538 ,  H01L2924/01044 ,  H01L2224/81 ,  H01L2224/83 ,  H01L21/78

摘要： The present invention provides a photosensitive resin composition comprising an alkali-soluble resin having a phenolic hydroxyl group as an end group (A); a radiation-polymerizable compound (B); and a photoinitiator (C), a film adhesive, an adhesive sheet, an adhesive pattern, a semiconductor wafer with an adhesive layer, and a semiconductor device using the photosensitive resin composition.

摘要翻译： 本发明提供一种包含具有酚羟基作为端基（A）的碱溶性树脂的感光性树脂组合物。 辐射聚合性化合物（B）; 和光敏引发剂（C），胶粘剂，粘合片，粘合剂图案，具有粘合剂层的半导体晶片，以及使用该感光性树脂组合物的半导体装置。

公开(公告)号：US20130309861A1

公开(公告)日：2013-11-21

申请号：US13952481

申请日：2013-07-26

申请人： Micron Technology, Inc.

发明人： Jaspreet S. Gandhi

IPC分类号： H01L21/768

CPC分类号： H01L24/14 ,  H01L21/6835 ,  H01L21/7684 ,  H01L21/76898 ,  H01L23/3171 ,  H01L23/3192 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/03462 ,  H01L2224/0347 ,  H01L2224/0361 ,  H01L2224/03825 ,  H01L2224/0384 ,  H01L2224/03845 ,  H01L2224/03914 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/05016 ,  H01L2224/05018 ,  H01L2224/05019 ,  H01L2224/05022 ,  H01L2224/05023 ,  H01L2224/05025 ,  H01L2224/0508 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05555 ,  H01L2224/05556 ,  H01L2224/05564 ,  H01L2224/05568 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/11622 ,  H01L2224/1182 ,  H01L2224/1184 ,  H01L2224/13023 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2924/00014 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01044 ,  H01L2924/01046 ,  H01L2924/05042 ,  H01L2924/0538 ,  H01L2924/05442 ,  H01L2924/07025 ,  H01L2924/10253 ,  H01L2924/01029 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2224/05552

摘要： Some embodiments include a planarization method. A liner is formed across a semiconductor substrate and along posts that extending upwardly from the substrate. Organic fill material is formed over the liner and between the posts. A planarized surface is formed which extends across the posts and across one or both of the liner and the fill material. Some embodiments include a semiconductor construction containing a semiconductor die. Electrically conductive posts extend through the die. The posts have upper surfaces above a backside surface of the die, and have sidewall surfaces extending between the backside surface and the upper surfaces. A liner is across the backside surface of the die and along the sidewall surfaces of the posts. Electrically conductive caps are over the upper surfaces of the posts, and have rims along the liner adjacent the sidewall surfaces of the posts.

公开(公告)号：US20020093098A1

公开(公告)日：2002-07-18

申请号：US10051262

申请日：2002-01-18

发明人： Alexander L. Barr ,  Suresh Venkatesan ,  David B. Clegg ,  Rebecca G. Cole ,  Olubunmi Adetutu ,  Stuart E. Greer ,  Brian G. Anthony ,  Ramnath Venkatraman ,  Gregor Braeckelmann ,  Douglas M. Reber ,  Stephen R. Crown

IPC分类号： H01L029/40 ,  H01L023/52 ,  H01L023/48

CPC分类号： H01L21/76849 ,  H01L21/76801 ,  H01L21/76807 ,  H01L21/76813 ,  H01L21/76843 ,  H01L21/76877 ,  H01L23/53233 ,  H01L23/53238 ,  H01L24/11 ,  H01L24/13 ,  H01L2223/54473 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05024 ,  H01L2224/05025 ,  H01L2224/05027 ,  H01L2224/0508 ,  H01L2224/05147 ,  H01L2224/05157 ,  H01L2224/05166 ,  H01L2224/05172 ,  H01L2224/0518 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05186 ,  H01L2224/05572 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2924/0001 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01016 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01044 ,  H01L2924/01046 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01076 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/12042 ,  H01L2924/19041 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05169 ,  H01L2924/013 ,  H01L2924/0496 ,  H01L2924/0539 ,  H01L2924/0538 ,  H01L2924/0537

摘要： An interconnect overlies a semiconductor device substrate (10). In one embodiment, a conductive barrier layer overlies a portion of the interconnect, a passivation layer (92) overlies the conductive barrier layer and the passivation layer (92) has an opening that exposes portions of the conductive barrier layer (82). In an alternate embodiment a passivation layer (22) overlies the interconnect, the passivation layer (22) has an opening (24) that exposes the interconnect and a conductive barrier layer (32) overlies the interconnect within the opening (24).

摘要翻译： 互连覆盖半导体器件衬底（10）。 在一个实施例中，导电阻挡层覆盖在互连的一部分上，钝化层（92）覆盖在导电阻挡层上，钝化层（92）具有暴露导电阻挡层（82）的部分的开口。 在替代实施例中，钝化层（22）覆盖互连，钝化层（22）具有暴露互连的开口（24），并且导电阻挡层（32）覆盖开口（24）内的互连。

公开(公告)号：US09754905B1

公开(公告)日：2017-09-05

申请号：US15292433

申请日：2016-10-13

申请人： International Business Machines Corporation

发明人： Ekta Misra ,  Krishna R. Tunga

IPC分类号： H01L23/00

CPC分类号： H01L24/05 ,  H01L24/03 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/02126 ,  H01L2224/0215 ,  H01L2224/02166 ,  H01L2224/02185 ,  H01L2224/0219 ,  H01L2224/03013 ,  H01L2224/0401 ,  H01L2224/05073 ,  H01L2224/05082 ,  H01L2224/05083 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05191 ,  H01L2224/05611 ,  H01L2224/05616 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05657 ,  H01L2224/05666 ,  H01L2224/05669 ,  H01L2224/0567 ,  H01L2224/05676 ,  H01L2224/05681 ,  H01L2224/05684 ,  H01L2224/05687 ,  H01L2224/05691 ,  H01L2224/05693 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2924/07025 ,  H01L2924/3511 ,  H01L2924/35121 ,  H01L2924/014 ,  H01L2924/01047 ,  H01L2924/00014 ,  H01L2924/04953 ,  H01L2924/04941 ,  H01L2924/0455 ,  H01L2924/01073 ,  H01L2924/04541 ,  H01L2924/0469 ,  H01L2924/0463 ,  H01L2924/01013 ,  H01L2924/0476 ,  H01L2924/01074 ,  H01L2924/0496 ,  H01L2924/0538 ,  H01L2924/01044 ,  H01L2924/0479 ,  H01L2924/01027 ,  H01L2924/048 ,  H01L2924/01028 ,  H01L2924/01006

摘要： Embodiments are directed to a method of forming a semiconductor chip package and resulting structures having an annular PSPI region formed under a BLM pad. An annular region is formed under a barrier layer metallurgy (BLM) pad. The annular region includes a photosensitive polyimide (PSPI). A conductive pedestal is formed on a surface of the BLM pad and a solder bump is formed on a surface of the conductive pedestal. The annular PSPI region reduces wafer warpage and ULK peeling stress.

公开(公告)号：US20170133307A1

公开(公告)日：2017-05-11

申请号：US15159212

申请日：2016-05-19

申请人： STMicroelectronics S.r.l.

发明人： Federico Giovanni Ziglioli

IPC分类号： H01L23/498 ,  H01L21/48 ,  H01L23/00

CPC分类号： H01L23/49838 ,  H01L21/4846 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48227 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01044 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/0538 ,  H01L2924/06 ,  H01L2924/07025 ,  H01L2924/14 ,  H01L2924/15747 ,  H05K1/0287 ,  H05K1/0289 ,  H05K1/0295 ,  H05K1/112 ,  H05K3/107 ,  H05K3/205 ,  H05K3/4015 ,  H05K3/4046 ,  H05K2201/09409 ,  H05K2201/09945 ,  H05K2201/10378 ,  H05K2203/025 ,  H05K2203/0338 ,  H05K2203/0361 ,  H05K2203/0369 ,  H05K2203/1189 ,  H05K2203/143 ,  H05K2203/1461 ,  H05K2203/1476 ,  H05K2203/308 ,  H01L2224/45099

摘要： A substrate for mounting a semiconductor device includes an insulating layer having first and second opposed surfaces defining a thickness. First and second electrically conductive lands are included in the insulating layer. The first electrically conductive lands extend through the whole thickness of the insulating layer and are exposed on both the first and second opposed surfaces. The second electrically conductive lands have a thickness less than the thickness of the insulating layer and are exposed only at the first surface. Electrically conductive lines at the first surface of the insulating layer couple certain ones of the first electrically conductive lands with certain ones of the second electrically conductive lands. The semiconductor device is mounted to the first surface of the insulating layer. Wire bonding may be used to electrically coupling the semiconductor device to certain ones of the first and second lands.