公开(公告)号：US06713381B2

公开(公告)日：2004-03-30

申请号：US10051262

申请日：2002-01-18

申请人： Alexander L. Barr ,  Suresh Venkatesan ,  David B. Clegg ,  Rebecca G. Cole ,  Olubunmi Adetutu ,  Stuart E. Greer ,  Brian G. Anthony ,  Ramnath Venkatraman ,  Gregor Braeckelmann ,  Douglas M. Reber ,  Stephen R. Crown

发明人： Alexander L. Barr ,  Suresh Venkatesan ,  David B. Clegg ,  Rebecca G. Cole ,  Olubunmi Adetutu ,  Stuart E. Greer ,  Brian G. Anthony ,  Ramnath Venkatraman ,  Gregor Braeckelmann ,  Douglas M. Reber ,  Stephen R. Crown

IPC分类号： H01L214763

CPC分类号： H01L21/76849 ,  H01L21/76801 ,  H01L21/76807 ,  H01L21/76813 ,  H01L21/76843 ,  H01L21/76877 ,  H01L23/53233 ,  H01L23/53238 ,  H01L24/11 ,  H01L24/13 ,  H01L2223/54473 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05024 ,  H01L2224/05025 ,  H01L2224/05027 ,  H01L2224/0508 ,  H01L2224/05147 ,  H01L2224/05157 ,  H01L2224/05166 ,  H01L2224/05172 ,  H01L2224/0518 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05186 ,  H01L2224/05572 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2924/0001 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01016 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01044 ,  H01L2924/01046 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01076 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/12042 ,  H01L2924/19041 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05169 ,  H01L2924/013 ,  H01L2924/0496 ,  H01L2924/0539 ,  H01L2924/0538 ,  H01L2924/0537

摘要： An interconnect overlies a semiconductor device substrate (10). In one embodiment, a conductive barrier layer overlies a portion of the interconnect, a passivation layer (92) overlies the conductive barrier layer and the passivation layer (92) has an opening that exposes portions of the conductive barrier layer (82). In an alternate embodiment a passivation layer (22) overlies the interconnect, the passivation layer (22) has an opening (24) that exposes the interconnect and a conductive barrier layer (32) overlies the interconnect within the opening (24).

摘要翻译： 互连覆盖半导体器件衬底（10）。 在一个实施例中，导电阻挡层覆盖在互连的一部分上，钝化层（92）覆盖在导电阻挡层上，钝化层（92）具有暴露导电阻挡层（82）的部分的开口。 在替代实施例中，钝化层（22）覆盖互连，钝化层（22）具有暴露互连的开口（24），并且导电阻挡层（32）覆盖开口（24）内的互连。

公开(公告)号：US06573173B2

公开(公告)日：2003-06-03

申请号：US10175637

申请日：2002-06-20

申请人： Janos Farkas ,  Brian G. Anthony ,  Abbas Guvenilir ,  Mohammed Rabiul Islam ,  Venkat Kolagunta ,  John Mendonca ,  Rajesh Tiwari ,  Suresh Venkatesan

发明人： Janos Farkas ,  Brian G. Anthony ,  Abbas Guvenilir ,  Mohammed Rabiul Islam ,  Venkat Kolagunta ,  John Mendonca ,  Rajesh Tiwari ,  Suresh Venkatesan

IPC分类号： H01L214763

CPC分类号： H01L21/7684 ,  H01L21/02074 ,  H01L21/3212

摘要： A copper interconnect polishing process begins by polishing (17) a bulk thickness of copper (63) using a first platen. A second platen is then used to remove (19) a thin remaining interfacial copper layer to expose a barrier film (61). Computer control (21) monitors polish times of the first and second platen and adjusts these times to improve wafer throughput. One or more platens and/or the wafer is rinsed (20) between the interfacial copper polish and the barrier polish to reduce slurry cross contamination. A third platen and slurry is then used to polish away exposed portions of the barrier (61) to complete polishing of the copper interconnect structure. A holding tank that contains anti-corrosive fluid is used to queue the wafers until subsequent scrubbing operations (25). A scrubbing operation (25) that is substantially void of light is used to reduce photovoltaic induced corrosion of copper in the drying chamber of the scubber.

公开(公告)号：US06444569B1

公开(公告)日：2002-09-03

申请号：US09835276

申请日：2001-04-16

申请人： Janos Farkas ,  Brian G. Anthony ,  Abbas Guvenilir ,  Mohammed Rabiul Islam ,  Venkat Kolagunta ,  John Mendonca ,  Rajesh Tiwari ,  Suresh Venkatesan

发明人： Janos Farkas ,  Brian G. Anthony ,  Abbas Guvenilir ,  Mohammed Rabiul Islam ,  Venkat Kolagunta ,  John Mendonca ,  Rajesh Tiwari ,  Suresh Venkatesan

IPC分类号： H01L214763

摘要： A copper interconnect polishing process begins by polishing (17) a bulk thickness of copper (63) using a first platen. A second platen is then used to remove (19) a thin remaining interfacial copper layer to expose a barrier film (61). Computer control (21) monitors polish times of the first and second platen and adjusts these times to improve wafer throughput. One or more platens and/or the wafer is rinsed (20) between the interfacial copper polish and the barrier polish to reduce slurry cross contamination. A third platen and slurry is then used to polish away exposed portions of the barrier (61) to complete polishing of the copper interconnect structure. A holding tank that contains anti-corrosive fluid is used to queue the wafers until subsequent scrubbing operations (25). A scrubbing operation (25) that is substantially void of light is used to reduce photovoltaic induced corrosion of copper in the drying chamber of the scubber.

公开(公告)号：US06274478B1

公开(公告)日：2001-08-14

申请号：US09352136

申请日：1999-07-13

申请人： Janos Farkas ,  Brian G. Anthony ,  Abbas Guvenilir ,  Mohammed Rabiul Islam ,  Venkat Kolagunta ,  John Mendonca ,  Rajesh Tiwari ,  Suresh Venkatesan

发明人： Janos Farkas ,  Brian G. Anthony ,  Abbas Guvenilir ,  Mohammed Rabiul Islam ,  Venkat Kolagunta ,  John Mendonca ,  Rajesh Tiwari ,  Suresh Venkatesan

IPC分类号： H01L214763

CPC分类号： H01L21/7684 ,  H01L21/02074 ,  H01L21/31053 ,  H01L21/3212

摘要： A copper interconnect polishing process begins by polishing (17) a bulk thickness of copper (63) using a first platen. A second platen is then used to remove (19) a thin remaining interfacial copper layer to expose a barrier film (61). Computer control (21) monitors polish times of the first and second platen and adjusts these times to improve wafer throughput. One or more platens and/or the wafer is rinsed (20) between the interfacial copper polish and the barrier polish to reduce slurry cross contamination. A third platen and slurry is then used to polish away exposed portions of the barrier (61) to complete polishing of the copper interconnect structure. A holding tank that contains anti-corrosive fluid is used to queue the wafers until subsequent scrubbing operations (25). A scrubbing operation (25) that is substantially void of light is used to reduce photovoltaic induced corrosion of copper in the drying chamber of the scrubber.

摘要翻译： 铜互连抛光工艺通过使用第一压板抛光（17）铜（63）的体积厚度开始。 然后使用第二压板来去除（19）薄的剩余界面铜层以暴露阻挡膜（61）。 计算机控制（21）监测第一和第二压板的抛光时间并调整这些时间以提高晶片的吞吐量。 一个或多个压板和/或晶片在界面铜抛光剂和阻隔抛光剂之间漂洗（20），以减少淤浆交叉污染。 然后使用第三压板和浆料抛光掉屏障（61）的暴露部分以完成铜互连结构的抛光。 使用含有防腐蚀液体的储存罐将晶片排队，直到后续的擦洗操作（25）。 使用基本上无光的擦洗操作（25）用于减少洗涤器的干燥室中的铜的光伏诱发的腐蚀。

公开(公告)号：US09355910B2

公开(公告)日：2016-05-31

申请号：US13324740

申请日：2011-12-13

申请人： Mahbub Rashed ,  Irene Y. Lin ,  Steven Soss ,  Jeff Kim ,  Chinh Nguyen ,  Marc Tarabbia ,  Scott Johnson ,  Subramani Kengeri ,  Suresh Venkatesan

发明人： Mahbub Rashed ,  Irene Y. Lin ,  Steven Soss ,  Jeff Kim ,  Chinh Nguyen ,  Marc Tarabbia ,  Scott Johnson ,  Subramani Kengeri ,  Suresh Venkatesan

IPC分类号： H01L21/70 ,  H01L21/8234 ,  H01L27/02 ,  H01L21/768 ,  H01L27/118

CPC分类号： H01L23/535 ,  H01L21/28518 ,  H01L21/76895 ,  H01L21/823418 ,  H01L21/823475 ,  H01L21/823814 ,  H01L21/823871 ,  H01L23/53238 ,  H01L27/0207 ,  H01L27/092 ,  H01L27/11807 ,  H01L29/0847 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device is provided for implementing at least one logic element. The semiconductor device includes a semiconductor substrate with a first transistor and a second transistor formed on the semiconductor substrate. Each of the transistors comprises a source, a drain, and a gate. A trench silicide layer electrically connects one of the source or the drain of the first transistor to one of the source or the drain of the second transistor.

摘要翻译： 提供半导体器件用于实现至少一个逻辑元件。 该半导体器件包括具有第一晶体管的半导体衬底和形成在半导体衬底上的第二晶体管。 每个晶体管包括源极，漏极和栅极。 沟槽硅化物层将第一晶体管的源极或漏极之一电连接到第二晶体管的源极或漏极之一。

公开(公告)号：US20140042641A1

公开(公告)日：2014-02-13

申请号：US13568737

申请日：2012-08-07

申请人： Mahbub Rashed ,  Yuansheng Ma ,  Irene Lin ,  Jason Stephens ,  Yunfei Deng ,  Yuan Lei ,  Jongwook Kye ,  Rod Augur ,  Shibly Ahmed ,  Subramani Kengeri ,  Suresh Venkatesan

发明人： Mahbub Rashed ,  Yuansheng Ma ,  Irene Lin ,  Jason Stephens ,  Yunfei Deng ,  Yuan Lei ,  Jongwook Kye ,  Rod Augur ,  Shibly Ahmed ,  Subramani Kengeri ,  Suresh Venkatesan

IPC分类号： H01L21/768 ,  H01L23/48

CPC分类号： H01L23/5386 ,  H01L21/76895 ,  H01L21/823871 ,  H01L23/5384 ,  H01L27/0207 ,  H01L27/0924 ,  H01L29/7851 ,  H01L2924/0002 ,  H01L2924/00

摘要： An approach for providing MOL constructs using diffusion contact structures is disclosed. Embodiments include: providing a first diffusion region in a substrate; providing, via a first lithography process, a first diffusion contact structure; providing, via a second lithography process, a second diffusion contact structure; and coupling the first diffusion contact structure to the first diffusion region and the second diffusion contact structure. Embodiments include: providing a second diffusion region in the substrate; providing a diffusion gap region between the first and second diffusion regions; providing the diffusion contact structure over the diffusion gap region; and coupling, via the diffusion contact structure, the first and second diffusion regions.

摘要翻译： 公开了一种使用扩散接触结构提供MOL构造的方法。 实施例包括：在衬底中提供第一扩散区域; 通过第一光刻工艺提供第一扩散接触结构; 经由第二光刻工艺提供第二扩散接触结构; 以及将所述第一扩散接触结构耦合到所述第一扩散区和所述第二扩散接触结构。 实施例包括：在衬底中提供第二扩散区域; 在所述第一和第二扩散区之间提供扩散间隙区域; 在扩散间隙区域上提供扩散接触结构; 以及经由扩散接触结构耦合第一和第二扩散区域。

公开(公告)号：US08621074B2

公开(公告)日：2013-12-31

申请号：US13458327

申请日：2012-04-27

申请人： Faiyaz Shikari ,  Madhav Matta ,  Suresh Venkatesan

发明人： Faiyaz Shikari ,  Madhav Matta ,  Suresh Venkatesan

IPC分类号： G06F15/173

CPC分类号： H04L43/08 ,  G06F9/546 ,  G06F2209/548 ,  H04L67/10 ,  H04L67/1002 ,  H04L67/1008

摘要： A management system for processing message-based communications comprising a plurality of servers configured to implement a plurality of sessions that process a plurality of messages, a plurality of message queues coupled to the servers and configured to exchange the messages with the servers, and a workload manager coupled to the servers and the message queues and configured to reallocate the sessions to the different servers and the corresponding message queues to achieve load balance between the servers and the message queues in a recurring manner during processing of the messages by the servers based on a depth of each of the message queues, a quantity of sessions for each of the servers, and a workload manager configuration.

摘要翻译： 一种用于处理基于消息的通信的管理系统，包括被配置为实现处理多个消息的多个会话的多个服务器，耦合到所述服务器并被配置为与所述服务器交换消息的多个消息队列，以及工作负载 管理器耦合到服务器和消息队列，并被配置为将会话重新分配到不同的服务器和相应的消息队列，以在服务器基于以下情况处理消息期间以重复的方式实现服务器和消息队列之间的负载平衡 每个消息队列的深度，每个服务器的会话数量以及工作负载管理器配置。

公开(公告)号：US08618607B1

公开(公告)日：2013-12-31

申请号：US13539830

申请日：2012-07-02

申请人： Mahbub Rashed ,  David Doman ,  Marc Tarabbia ,  Irene Lin ,  Jeff Kim ,  Chinh Nguyen ,  Steve Soss ,  Scott Johnson ,  Subramani Kengeri ,  Suresh Venkatesan

发明人： Mahbub Rashed ,  David Doman ,  Marc Tarabbia ,  Irene Lin ,  Jeff Kim ,  Chinh Nguyen ,  Steve Soss ,  Scott Johnson ,  Subramani Kengeri ,  Suresh Venkatesan

IPC分类号： H01L21/02

CPC分类号： H01L27/0207 ,  H01L27/11807

摘要： One illustrative device disclosed herein includes a continuous active region defined in a semiconducting substrate, first and second transistors formed in and above the continuous active region, each of the first and second transistors comprising a plurality of doped regions formed in the continuous active region, a conductive isolating electrode positioned above the continuous active region between the first and second transistors and a power rail conductively coupled to the conductive isolating electrode.

摘要翻译： 本文公开的一个说明性器件包括限定在半导体衬底中的连续有源区，形成在连续有源区中和上方的第一和第二晶体管，第一和第二晶体管中的每一个包括形成在连续有源区中的多个掺杂区， 导电隔离电极位于第一和第二晶体管之间的连续有源区上方，导电隔离电极与导电隔离电极导电耦合。

公开(公告)号：US08598633B2

公开(公告)日：2013-12-03

申请号：US13351101

申请日：2012-01-16

申请人： Marc Tarabbia ,  James B. Gullette ,  Mahbub Rashed ,  David S. Doman ,  Irene Y. Lin ,  Ingolf Lorenz ,  Larry Ho ,  Chinh Nguyen ,  Jeff Kim ,  Jongwook Kye ,  Yuansheng Ma ,  Yunfei Deng ,  Rod Augur ,  Seung-Hyun Rhee ,  Jason E. Stephens ,  Scott Johnson ,  Subramani Kengeri ,  Suresh Venkatesan

发明人： Marc Tarabbia ,  James B. Gullette ,  Mahbub Rashed ,  David S. Doman ,  Irene Y. Lin ,  Ingolf Lorenz ,  Larry Ho ,  Chinh Nguyen ,  Jeff Kim ,  Jongwook Kye ,  Yuansheng Ma ,  Yunfei Deng ,  Rod Augur ,  Seung-Hyun Rhee ,  Jason E. Stephens ,  Scott Johnson ,  Subramani Kengeri ,  Suresh Venkatesan

IPC分类号： H01L23/52

CPC分类号： H01L23/5286 ,  H01L21/76895 ,  H01L21/823475 ,  H01L27/088 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device includes a semiconductor substrate having a diffusion region. A transistor is formed within the diffusion region. A power rail is disposed outside the diffusion region. A contact layer is disposed above the substrate and below the power rail. A via is disposed between the contact layer and the power rail to electrically connect the contact layer to the power rail. The contact layer includes a first length disposed outside the diffusion region and a second length extending from the first length into the diffusion region and electrically connected to the transistor.

摘要翻译： 半导体器件包括具有扩散区域的半导体衬底。 晶体管形成在扩散区内。 电力轨设置在扩散区域的外侧。 接触层设置在基板上方和电源轨下方。 通孔设置在接触层和电源轨之间以将接触层电连接到电源轨。 接触层包括设置在扩散区域外部的第一长度和从第一长度延伸到扩散区域并电连接到晶体管的第二长度。

公开(公告)号：US5736435A

公开(公告)日：1998-04-07

申请号：US497317

申请日：1995-07-03

申请人： Suresh Venkatesan ,  Stephen Poon ,  Jeffrey Lutze ,  Sergio Ajuria

发明人： Suresh Venkatesan ,  Stephen Poon ,  Jeffrey Lutze ,  Sergio Ajuria

IPC分类号： H01L21/336 ,  H01L21/84 ,  H01L29/786 ,  H01L21/00 ,  H01L21/3205

CPC分类号： H01L29/66772 ,  H01L21/84 ,  H01L29/78618 ,  H01L29/78648

摘要： A process for fabricating a MOSFET on an SOI substrate includes the formation of an active region (14) isolated by field isolation regions (16, 18) and by an insulating layer (12). A recess (26) is formed in the active region (14) using a masking layer (22) having an opening (24) therein. A gate dielectric layer (32) is formed in the recess (26) and a polycrystalline silicon layer (34) is deposited to overlie the masking layer (22), and to fill the recess (26). A planarization process is carried out to form a gate electrode (36) in the recess (26), and source and drain regions (40, 42) are formed in a self-aligned manner to the gate electrode (36). A channel region (44) resides intermediate to the source and drain regions (40, 42) and directly below the gate electrode (36).

摘要翻译： 在SOI衬底上制造MOSFET的工艺包括形成由场隔离区域（16,18）和绝缘层（12）隔离的有源区域（14）。 使用其中具有开口（24）的掩模层（22）在有源区域（14）中形成凹部（26）。 在凹部（26）中形成栅介电层（32），沉积多晶硅层（34）以覆盖掩模层（22）并填充凹部（26）。 进行平面化处理以在凹部（26）中形成栅电极（36），并且源极和漏极区域（40,42）以与栅电极（36）自对准的方式形成。 通道区域（44）位于源极和漏极区域（40,42）的中间，并且位于栅电极（36）的正下方。