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公开(公告)号：US20050007490A1
公开(公告)日：2005-01-13
申请号：US10611451
申请日：2003-06-30
申请人： Alexander MacInnis , Greg Kranawetter , Sandeep Bhatia , Shen-Yung Chen , Mahadhevan Sivagururaman , D. Srilakshmi
发明人： Alexander MacInnis , Greg Kranawetter , Sandeep Bhatia , Shen-Yung Chen , Mahadhevan Sivagururaman , D. Srilakshmi
CPC分类号： H04N7/012 , H04N5/4401 , H04N7/01 , H04N7/0122 , H04N21/440218
摘要： Presented herein are a system, method, and apparatus for improving scaling with early deinterlacing. Interlaced frames are deinterlaced prior to scaling. Accordingly, the scaler scales an entire frame, in contrast to individual fields, thereby resulting in an improved scaling function.
摘要翻译： 这里提出的是用于使用早期去隔行来改进缩放的系统，方法和装置。 隔行扫描帧在缩放之前被去隔行扫描。 因此，与单个场相反，缩放器缩放整个帧，由此导致改进的缩放功能。
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公开(公告)号：US20070216808A1
公开(公告)日：2007-09-20
申请号：US11550755
申请日：2006-10-18
申请人： Alexander MacInnis , Greg Kranawetter , Sandeep Bhatia , Robin (Shen-yung) Chen , Mahadhevan Sivagururaman , Srilakshmi Dorarajulu
发明人： Alexander MacInnis , Greg Kranawetter , Sandeep Bhatia , Robin (Shen-yung) Chen , Mahadhevan Sivagururaman , Srilakshmi Dorarajulu
IPC分类号： H04N7/00
CPC分类号： H04N7/0112 , H04N7/012
摘要： Presented herein are systems and methods for scaling. In one embodiment, there is presented a method for scaling. The method comprises receiving a top field and a bottom field, detecting whether the top field and bottom field correspond to the same time period, and generating a scaled field for display using both the top field and bottom field, if the top field and the bottom field correspond to the same time period.
摘要翻译： 这里提出的是用于缩放的系统和方法。 在一个实施例中，提出了一种缩放方法。 该方法包括接收顶场和底场，检测顶场和底场是否对应于相同的时间段，并且如果顶场和底场都使用顶场和底场，则生成用于显示的缩放场 字段对应于相同的时间段。
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公开(公告)号：US20050122335A1
公开(公告)日：2005-06-09
申请号：US10997652
申请日：2004-11-23
申请人： Alexander MacInnis , Chengfuh Tang , Xiaodong Xie , Greg Kranawetter , Vivian Hsiun , Francis Cheung , Sandeep Bhatia , Ramanujan Valmiki , Sathish Kumar
发明人： Alexander MacInnis , Chengfuh Tang , Xiaodong Xie , Greg Kranawetter , Vivian Hsiun , Francis Cheung , Sandeep Bhatia , Ramanujan Valmiki , Sathish Kumar
IPC分类号： G06T9/00 , G09G1/16 , G09G5/00 , G09G5/02 , G09G5/06 , G09G5/12 , G09G5/14 , G09G5/28 , G09G5/34 , G09G5/36 , G09G5/39 , G09G5/395 , G09G5/397 , G09G5/42 , H04N5/14 , H04N5/44 , H04N5/445 , H04N5/45 , H04N5/46 , H04N7/01 , H04N9/45 , H04N9/64 , H04N11/14 , H04N11/20 , H04N21/426 , H04N21/43 , H04N21/431 , H04N21/434 , H04N21/4402 , H04N21/443 , H04N21/81 , G06F13/14
CPC分类号： H04N9/641 , G06T9/007 , G09G5/001 , G09G5/008 , G09G5/02 , G09G5/024 , G09G5/026 , G09G5/06 , G09G5/12 , G09G5/14 , G09G5/28 , G09G5/346 , G09G5/36 , G09G5/363 , G09G2310/0224 , G09G2320/0247 , G09G2340/02 , G09G2340/0407 , G09G2340/10 , G09G2340/125 , G09G2350/00 , G09G2360/02 , G09G2360/121 , G09G2360/125 , G09G2360/126 , G09G2360/128 , H04N5/14 , H04N5/4401 , H04N5/44504 , H04N5/44508 , H04N5/45 , H04N5/46 , H04N7/0135 , H04N9/45 , H04N11/00 , H04N11/143 , H04N11/20 , H04N11/22 , H04N21/42653 , H04N21/42692 , H04N21/4305 , H04N21/4316 , H04N21/4345 , H04N21/4348 , H04N21/440218 , H04N21/4435 , H04N21/8146
摘要： A video, audio and graphics system uses multiple transport processors to receive in-band and out-of-band MPEG Transport streams, to perform PID and section filtering as well as DVB and DES decryption and to de-multiplex them. The system processes the PES into digital audio, MPEG video and message data. The system is capable of decoding multiple MPEG SLICEs concurrently. Graphics windows are blended in parallel, and blended with video using alpha blending. During graphics processing, a single-port SRAM is used equivalently as a dual-port SRAM. The video may include both analog video, e.g., NTSC/PAL/SECAM/S-video, and digital video, e.g., MPEG-2 video in SDTV or HDTV format. The system has a reduced memory mode in which video images are reduced in half in horizontal direction only during decoding. The system is capable of receiving and processing digital audio signals such as MPEG Layer 1 and Layer 2 audio and Dolby AC-3 audio, as well as PCM audio signals. The system includes a memory controller. The system includes a system bridge controller to interface a CPU with devices internal to the system as well as peripheral devices including PCI devices and I/O devices such as RAM, ROM and flash memory devices. The system is capable of displaying video and graphics in both the high definition (HD) mode and the standard definition (SD) mode. The system may output an HDTV video while converting the HDTV video and providing as another output having an SDTV format or another HDTV format.
摘要翻译： 视频，音频和图形系统使用多个传输处理器来接收带内和带外MPEG传输流，以执行PID和部分滤波以及DVB和DES解密，并对其进行解复用。 该系统将PES处理成数字音频，MPEG视频和消息数据。 该系统能够同时解码多个MPEG SLICE。 图形窗口并行混合，并使用alpha混合与视频混合。 在图形处理期间，单端口SRAM被等价地用作双端口SRAM。 视频可以包括模拟视频，例如NTSC / PAL / SECAM / S视频和数字视频，例如SDTV或HDTV格式的MPEG-2视频。 该系统具有减小的存储模式，其中仅在解码期间视频图像在水平方向上减少一半。 该系统能够接收和处理数字音频信号，如MPEG第1层和第2层音频和杜比AC-3音频以及PCM音频信号。 该系统包括一个内存控制器。 该系统包括系统桥接控制器，用于将CPU与系统内部的设备以及包括PCI设备和诸如RAM，ROM和闪存设备的I / O设备的外围设备连接。 该系统能够在高清（HD）模式和标准清晰度（SD）模式下显示视频和图形。 该系统可以在转换HDTV视频的同时输出HDTV视频，并提供具有SDTV格式或另一HDTV格式的另一输出。
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公开(公告)号：US20060268012A1
公开(公告)日：2006-11-30
申请号：US11498595
申请日：2006-08-03
申请人： Alexander MacInnis , Chengfuh Tang , Xiaodong Xie , Greg Kranawetter , Vivian Hsiun , Francis Cheung , Sandeep Bhatia , Ramanujan Valmiki , Sathish Kumar
发明人： Alexander MacInnis , Chengfuh Tang , Xiaodong Xie , Greg Kranawetter , Vivian Hsiun , Francis Cheung , Sandeep Bhatia , Ramanujan Valmiki , Sathish Kumar
IPC分类号： G09G5/00
CPC分类号： H04N9/641 , G06T9/007 , G09G5/001 , G09G5/008 , G09G5/02 , G09G5/024 , G09G5/026 , G09G5/06 , G09G5/12 , G09G5/14 , G09G5/28 , G09G5/346 , G09G5/36 , G09G5/363 , G09G2310/0224 , G09G2320/0247 , G09G2340/02 , G09G2340/0407 , G09G2340/10 , G09G2340/125 , G09G2350/00 , G09G2360/02 , G09G2360/121 , G09G2360/125 , G09G2360/126 , G09G2360/128 , H04N5/14 , H04N5/4401 , H04N5/44504 , H04N5/44508 , H04N5/45 , H04N5/46 , H04N7/0135 , H04N9/45 , H04N11/00 , H04N11/143 , H04N11/20 , H04N11/22 , H04N21/42653 , H04N21/42692 , H04N21/4305 , H04N21/4316 , H04N21/4345 , H04N21/4348 , H04N21/440218 , H04N21/4435 , H04N21/8146
摘要： A video, audio and graphics system uses multiple transport processors to receive in-band and out-of-band MPEG Transport streams, to perform PID and section filtering as well as DVB and DES decryption and to de-multiplex them. The system processes the PES into digital audio, MPEG video and message data. The system is capable of decoding multiple MPEG SLICEs concurrently. Graphics windows are blended in parallel, and blended with video using alpha blending. During graphics processing, a single-port SRAM is used equivalently as a dual-port SRAM. The video may include both analog video, e.g., NTSC/PAL/SECAM/S-video, and digital video, e.g., MPEG-2 video in SDTV or HDTV format. The system has a reduced memory mode in which video images are reduced in half in horizontal direction only during decoding. The system is capable of receiving and processing digital audio signals such as MPEG Layer 1 and Layer 2 audio and Dolby AC-3 audio, as well as PCM audio signals. The system includes a memory controller. The system includes a system bridge controller to interface a CPU with devices internal to the system as well as peripheral devices including PCI devices and I/O devices such as RAM, ROM and flash memory devices. The system is capable of displaying video and graphics in both the high definition (HD) mode and the standard definition (SD) mode. The system may output an HDTV video while converting the HDTV video and providing as another output having an SDTV format or another HDTV format.
摘要翻译： 视频，音频和图形系统使用多个传输处理器来接收带内和带外MPEG传输流，以执行PID和部分滤波以及DVB和DES解密，并对其进行解复用。 该系统将PES处理成数字音频，MPEG视频和消息数据。 该系统能够同时解码多个MPEG SLICE。 图形窗口并行混合，并使用alpha混合与视频混合。 在图形处理期间，单端口SRAM被等价地用作双端口SRAM。 视频可以包括模拟视频，例如NTSC / PAL / SECAM / S视频和数字视频，例如SDTV或HDTV格式的MPEG-2视频。 该系统具有减小的存储模式，其中仅在解码期间视频图像在水平方向上减少一半。 该系统能够接收和处理数字音频信号，如MPEG第1层和第2层音频和杜比AC-3音频以及PCM音频信号。 该系统包括一个内存控制器。 该系统包括系统桥接控制器，用于将CPU与系统内部的设备以及包括PCI设备和诸如RAM，ROM和闪存设备的I / O设备的外围设备连接。 该系统能够在高清（HD）模式和标准清晰度（SD）模式下显示视频和图形。 该系统可以在转换HDTV视频的同时输出HDTV视频，并提供具有SDTV格式或另一HDTV格式的另一输出。
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公开(公告)号：US20050175082A1
公开(公告)日：2005-08-11
申请号：US11025327
申请日：2004-12-29
申请人： Jason Herrick , Darren Neuman , Greg Kranawetter , Sandeep Bhatia
发明人： Jason Herrick , Darren Neuman , Greg Kranawetter , Sandeep Bhatia
IPC分类号： H04N7/01
CPC分类号： H04N19/46
摘要： A system and method that support display of video fields using related data encoded in data structures. Each data structure is associated with one video field and contains all the information associated with the display of the video field. The data structure is encoded with the video field that is displayed exactly one field prior to the field associated with the data structure. In an embodiment of the present invention, the data structure contains all the information associated with the display of a video field, regardless of whether certain data changes from one field to the next.
摘要翻译： 支持使用在数据结构中编码的相关数据来显示视频场的系统和方法。 每个数据结构与一个视频字段相关联并且包含与视频字段的显示相关联的所有信息。 数据结构使用在与数据结构相关联的字段之前正好显示一个字段的视频字段进行编码。 在本发明的实施例中，数据结构包含与视频字段的显示相关联的所有信息，而不管特定数据是否从一个字段改变到下一个字段。
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公开(公告)号：US20050028220A1
公开(公告)日：2005-02-03
申请号：US10791686
申请日：2004-03-03
申请人： David Baer , Jeff Tingley , Aleksandr Movshovich , Brad Grossman , Brian Schoner , Chengfuh Tang , Chuck Monahan , Darren Neuman , David Wu , Francis Cheung , Greg Kranawetter , Hoang Nhu , Hsien-Chih Tseng , Iue-Shuenn Chen , James Sweet , Jeffrey Bauch , Keith Klingler , Patrick Law , Rajesh Mamidwar , Dan Simon , Sang Tran , Shawn Johnson , Steven Jaffe , Thu Nguyen , Ut Nguyen , Yao-Hua Tseng , Brad Delanghe , Ben Giese , Jason Demas , Lakshman Ramakrishnan , Sandeep Bhatia , Guang-Ting Shih , Tracy Denk
发明人： David Baer , Jeff Tingley , Aleksandr Movshovich , Brad Grossman , Brian Schoner , Chengfuh Tang , Chuck Monahan , Darren Neuman , David Wu , Francis Cheung , Greg Kranawetter , Hoang Nhu , Hsien-Chih Tseng , Iue-Shuenn Chen , James Sweet , Jeffrey Bauch , Keith Klingler , Patrick Law , Rajesh Mamidwar , Dan Simon , Sang Tran , Shawn Johnson , Steven Jaffe , Thu Nguyen , Ut Nguyen , Yao-Hua Tseng , Brad Delanghe , Ben Giese , Jason Demas , Lakshman Ramakrishnan , Sandeep Bhatia , Guang-Ting Shih , Tracy Denk
CPC分类号： H04N21/426 , H04N5/4401 , H04N5/44504 , H04N5/46 , H04N7/035 , H04N21/4263 , H04N21/4305 , H04N2005/91364
摘要： A television on a chip (TVOC) system that provides a cost effective approach for providing television functionality on a single integrated circuit chip is disclosed. A TVOC includes the functionality necessary to receive and display television signals in a variety of input and output formats. A TVOC can be used in set-top boxes for cable and satellite television, or directly within a television. All functionality provided can be provided on a single integrated circuit. TVOC includes a data transport module, an IF demodulator, a digital audio engine, an analog audio engine, a digital video engine, and an analog video engine. The TVOC also includes three sets of interfaces including output interfaces, control interfaces and ancillary interfaces. Further features and embodiments provide enhanced functionality and increased efficiencies.
摘要翻译： 公开了一种提供用于在单个集成电路芯片上提供电视功能的成本有效方法的芯片上的电视（TVOC）系统。 TVOC包括以各种输入和输出格式接收和显示电视信号所必需的功能。 TVOC可用于有线和卫星电视的机顶盒，或直接在电视机内使用。 所提供的所有功能可以在单个集成电路上提供。 TVOC包括数据传输模块，IF解调器，数字音频引擎，模拟音频引擎，数字视频引擎和模拟视频引擎。 TVOC还包括三套接口，包括输出接口，控制接口和辅助接口。 其他特征和实施例提供增强的功能和提高的效率。
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公开(公告)号：US20080094506A1
公开(公告)日：2008-04-24
申请号：US11959139
申请日：2007-12-18
IPC分类号： H04N7/01
CPC分类号： G06F3/0611 , G06F3/0653 , G06F3/0659 , G06F3/0683 , G06T1/20 , G06T1/60 , G06T9/00 , G06T9/007 , G09G5/001 , G09G5/02 , G09G5/024 , G09G5/026 , G09G5/06 , G09G5/12 , G09G5/14 , G09G5/28 , G09G5/346 , G09G5/36 , G09G5/363 , G09G2310/0224 , G09G2320/0247 , G09G2340/02 , G09G2340/0407 , G09G2340/10 , G09G2340/125 , G09G2360/02 , G09G2360/121 , G09G2360/125 , G09G2360/126 , G09G2360/128 , H04N5/04 , H04N5/126 , H04N5/14 , H04N5/4401 , H04N5/44504 , H04N5/44508 , H04N5/44591 , H04N5/45 , H04N5/46 , H04N7/0122 , H04N7/0135 , H04N9/45 , H04N9/641 , H04N9/642 , H04N11/143 , H04N11/20 , H04N19/42 , H04N19/423 , H04N19/436 , H04N19/44 , H04N19/59 , H04N19/61 , H04N21/42204 , H04N21/42653 , H04N21/4305 , H04N21/4316 , H04N21/434 , H04N21/440263 , H04N21/4438 , H04N21/47
摘要： A graphics integrated circuit chip is used in a set-top box for controlling a television display. The graphics chip processes analog video input, digital video input, and graphics input. The chip includes a single polyphase filter that preferably provides both anti-flutter filtering and scaling of graphics. Anti-flutter filtering may help reduce display flicker due to the interlaced nature of television displays. The scaling of graphics may be used to convert the normally square pixel aspect ratio of graphics to the normally rectangular pixel aspect ratio of video.
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8.发明申请Graphics display system with anti-flutter filtering and vertical and vertical scaling feature 有权图形显示系统具有防颤滤波和垂直和垂直缩放功能公开(公告)号：US20050168480A1
公开(公告)日：2005-08-04
申请号：US11097028
申请日：2005-03-31
IPC分类号： G06T9/00 , G09G1/16 , G09G5/00 , G09G5/02 , G09G5/06 , G09G5/12 , G09G5/14 , G09G5/28 , G09G5/34 , G09G5/36 , G09G5/39 , G09G5/395 , G09G5/42 , H04N5/12 , H04N5/14 , H04N5/44 , H04N5/445 , H04N5/45 , H04N5/46 , H04N7/01 , H04N7/26 , H04N7/50 , H04N9/45 , H04N9/64 , H04N11/14 , H04N11/20 , H04N21/422 , H04N21/426 , H04N21/43 , H04N21/431 , H04N21/434 , H04N21/4402 , H04N21/443 , H04N21/47
CPC分类号： G06F3/0611 , G06F3/0653 , G06F3/0659 , G06F3/0683 , G06T1/20 , G06T1/60 , G06T9/00 , G06T9/007 , G09G5/001 , G09G5/02 , G09G5/024 , G09G5/026 , G09G5/06 , G09G5/12 , G09G5/14 , G09G5/28 , G09G5/346 , G09G5/36 , G09G5/363 , G09G2310/0224 , G09G2320/0247 , G09G2340/02 , G09G2340/0407 , G09G2340/10 , G09G2340/125 , G09G2360/02 , G09G2360/121 , G09G2360/125 , G09G2360/126 , G09G2360/128 , H04N5/04 , H04N5/126 , H04N5/14 , H04N5/4401 , H04N5/44504 , H04N5/44508 , H04N5/44591 , H04N5/45 , H04N5/46 , H04N7/0122 , H04N7/0135 , H04N9/45 , H04N9/641 , H04N9/642 , H04N11/143 , H04N11/20 , H04N19/42 , H04N19/423 , H04N19/436 , H04N19/44 , H04N19/59 , H04N19/61 , H04N21/42204 , H04N21/42653 , H04N21/4305 , H04N21/4316 , H04N21/434 , H04N21/440263 , H04N21/4438 , H04N21/47
摘要： A graphics integrated circuit chip is used in a set-top box for controlling a television display. The graphics chip processes analog video input, digital video input, and graphics input. The chip includes a single polyphase filter that preferably provides both anti-flutter filtering and scaling of graphics. Anti-flutter filtering may help reduce display flicker due to the interlaced nature of television displays. The scaling of graphics may be used to convert the normally square pixel aspect ratio of graphics to the normally rectangular pixel aspect ratio of video.
摘要翻译： 在用于控制电视显示器的机顶盒中使用图形集成电路芯片。 图形芯片处理模拟视频输入，数字视频输入和图形输入。 该芯片包括单个多相滤波器，其优选地提供图像的防颤音滤波和缩放。 防颤音滤波可能有助于减少由于电视显示器的隔行特性引起的显示闪烁。 图形的缩放可以用于将图形的正方形像素长宽比转换为视频的正常矩形像素长宽比。
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公开(公告)号：US20070120874A1
公开(公告)日：2007-05-31
申请号：US11441782
申请日：2006-05-26
IPC分类号： G09G5/00
CPC分类号： G09G5/001 , G09G5/06 , G09G5/12 , G09G5/14 , G09G5/28 , G09G5/346 , G09G5/363 , G09G5/395 , G09G2310/0224 , G09G2320/0247 , G09G2340/0407 , G09G2340/10 , G09G2340/125 , G09G2360/121 , G09G2360/125
摘要： A graphics integrated circuit chip is used in a set-top box for controlling a television display. The graphics chip processes analog video input, digital video input, a graphics input and an audio input simultaneously. The chip includes a display engine that processes graphics images organized as windows. The system includes plurality of line buffers for receiving the graphics contents. The graphics contents are composited into each of the plurality of line buffers by blending the graphics contents with the existing contents of the line buffer until all of the graphics surfaces for the line have been composited.
摘要翻译： 在用于控制电视显示器的机顶盒中使用图形集成电路芯片。 图形芯片同时处理模拟视频输入，数字视频输入，图形输入和音频输入。 该芯片包括一个显示引擎，用于处理组织为Windows的图形图像。 该系统包括用于接收图形内容的多个行缓冲器。 将图形内容通过将图形内容与行缓冲存储器的现有内容进行混合直到所有行的所有图形表面都被合成，来合成到多个行缓冲器的每一行中。
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公开(公告)号：US20070030276A1
公开(公告)日：2007-02-08
申请号：US11485582
申请日：2006-07-12
IPC分类号： G06F15/80
CPC分类号： G06T9/007 , G09G5/001 , G09G5/02 , G09G5/024 , G09G5/026 , G09G5/06 , G09G5/12 , G09G5/14 , G09G5/28 , G09G5/346 , G09G5/36 , G09G5/363 , G09G2300/0408 , G09G2310/0224 , G09G2320/0247 , G09G2340/02 , G09G2340/0407 , G09G2340/0428 , G09G2340/06 , G09G2340/10 , G09G2340/12 , G09G2340/125 , G09G2360/02 , G09G2360/121 , G09G2360/125 , G09G2360/126 , G09G2360/128 , H04N5/126 , H04N5/14 , H04N5/4401 , H04N5/44504 , H04N5/44508 , H04N5/44591 , H04N5/45 , H04N5/46 , H04N9/45 , H04N9/641 , H04N9/642 , H04N9/75 , H04N9/78 , H04N11/143 , H04N11/20 , H04N19/112 , H04N19/16 , H04N19/186 , H04N19/20 , H04N19/27 , H04N19/42 , H04N19/423 , H04N19/436 , H04N19/44 , H04N19/59 , H04N19/61 , H04N19/80 , H04N21/42204 , H04N21/42653 , H04N21/4305 , H04N21/4316 , H04N21/434 , H04N21/4438 , H04N21/47
摘要： A display engine of a video and graphics system includes one or more processing elements and receives graphics from a memory. The graphics data define multiple graphics layers, and the processing elements process two or more graphics layers in parallel to generate blended graphics. Alpha values may be used while blending graphics. The processing elements may be integrated on an integrated circuit chip with an input for receiving the graphics data and other video and graphics components. The display engine may also include a graphics controller for receiving two or more graphics layers in parallel, for arranging the graphics layers in an order suitable for parallel processing, and for providing the arranged graphics layers to the processing elements. The blended graphics may be blended with HDTV video or SDTV video, which may be extracted from compressed data streams such as an MPEG Transport stream.
摘要翻译： 视频和图形系统的显示引擎包括一个或多个处理元件并从存储器接收图形。 图形数据定义多个图形层，并且处理元件并行处理两个或多个图形层以产生混合图形。 混合图形时可以使用Alpha值。 处理元件可以集成在具有用于接收图形数据和其他视频和图形部件的输入的集成电路芯片上。 显示引擎还可以包括用于并行接收两个或更多图形层的图形控制器，用于以适于并行处理的顺序排列图形层，以及为处理元件提供布置的图形层。 混合图形可以与HDTV视频或SDTV视频混合，HDTV视频或SDTV视频可以从诸如MPEG传输流的压缩数据流中提取。
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