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1.发明授权
公开(公告)号：US5920487A
公开(公告)日：1999-07-06
申请号：US810561
申请日：1997-03-03
申请人： Alfred J. Reich , Warren D. Grobman , Bernard J. Roman , Kevin D. Lucas , Clyde H. Browning , Michael E. Kling
发明人： Alfred J. Reich , Warren D. Grobman , Bernard J. Roman , Kevin D. Lucas , Clyde H. Browning , Michael E. Kling
CPC分类号： G03F1/36 , G03F7/70441 , G06F17/5068
摘要： Integrated circuit designs are continually shrinking in size. Lithographic processes are used to transfer these designs to a semiconductor substrate. These processes typically require that the exposure wavelength of light be shorter than the smallest dimension of the elements within the circuit design. When this is not the case, exposure energy such as light behaves more like a wave than a particle. Additionally, mask manufacturing, photoresist chemical diffusion, and etch effects cause pattern transfer distortions. The result is that circuit elements do not print as designed. To counter this effect the circuit designs themselves can be altered so that the final printed results better matches the initial desired design. The process of altering designs in this way is called Lithographic Proximity Correction (LPC). Square (142), cross (162), octagon (172), and hammerhead (202) serifs are added to integrated circuit designs by shape manipulation functions to perform two dimensional (2-D) LPC.
摘要翻译： 集成电路设计的尺寸不断缩小。 使用平版印刷工艺将这些设计转移到半导体衬底。 这些过程通常要求光的曝光波长比电路设计中的元件的最小尺寸短。 当不是这样的情况下，诸如光的曝光能量比颗粒更像波浪。 另外，掩模制造，光致抗蚀剂化学扩散和蚀刻效应引起图案转印失真。 结果是电路元件不按照设计打印。 为了克服这种影响，电路设计本身可以被改变，使得最终的印刷结果更好地符合初始期望的设计。 以这种方式改变设计的过程称为光刻邻近校正（LPC）。 通过形状操作功能将方形（142），十字（162），八边形（172）和锤头（202）衬线添加到集成电路设计中以执行二维（2-D）LPC。
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2.发明授权
公开(公告)号：US5900340A
公开(公告)日：1999-05-04
申请号：US805863
申请日：1997-03-03
CPC分类号： G03F7/70441 , G03F1/36
摘要： Integrated circuit designs are continually shrinking in size. Lithographic processes are used to pattern these designs onto a semiconductor substrate. These processes typically require that the wavelength of exposure used during printing be significantly shorter than the smallest dimension of the elements within the circuit design. When this is not the case, the exposure radiation behaves more like a wave than a particle. Additionally, mask manufacturing, photoresist chemical diffusion and etch effects cause pattern transfer distortions. The result is that circuit elements do not print as designed. To counter this effect the designs themselves can be altered so that the final printed results better match the initial desired design. The process of altering designs in this way is called Lithographic Proximity Correction (LPC). Edge assist shapes and edge biasing features are added to integrated circuit designs by shape manipulation functions to perform one dimensional (1-D) LPC.
摘要翻译： 集成电路设计的尺寸不断缩小。 使用平版印刷工艺将这些设计图案化成半导体衬底。 这些工艺通常要求印刷期间使用的曝光波长明显短于电路设计中元件的最小尺寸。 当不是这种情况时，曝光辐射的行为比颗粒更像波。 此外，掩模制造，光致抗蚀剂化学扩散和蚀刻效果引起图案转印失真。 结果是电路元件不按照设计打印。 为了抵消这种影响，设计本身可以被改变，使得最终的印刷结果更好地符合初始期望的设计。 以这种方式改变设计的过程称为光刻邻近校正（LPC）。 通过形状操作功能将边缘辅助形状和边缘偏置特征添加到集成电路设计中，以执行一维（1-D）LPC。
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公开(公告)号：US06605395B2
公开(公告)日：2003-08-12
申请号：US09885575
申请日：2001-06-20
申请人： Warren D. Grobman , Ruoping Wang , Alfred J. Reich
发明人： Warren D. Grobman , Ruoping Wang , Alfred J. Reich
IPC分类号： G03F900
CPC分类号： G03F1/34
摘要： A method of patterning a wafer using four areas with differing exposure characteristics is disclosed. Two areas are phase shifted relative to the other two areas in order to create unexposed areas on the integrated circuit. Two different areas have polarizations orthogonal to each other, are frequency shifted relative to the two other areas, or are exposed by light at a time different than the two other areas to form exposed areas on the integrated circuit. The exposed areas are subsequently removed from the integrated circuit. In one embodiment, the four areas are on the same mask. The use of four areas with differing exposure characteristics allows for the patterning of more complicated and smaller geometric patterns on the integrated circuit than traditional patterning methods.
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公开(公告)号：US4622095A
公开(公告)日：1986-11-11
申请号：US789235
申请日：1985-10-18
CPC分类号： C23F4/02
摘要： A method of radiation induced dry etching of a metallized (e.g. copper) substrate is disclosed wherein the substrate is pattern-wise exposed to a beam of laser radiation in a halogen gas atmosphere which is reactive with the substrate to form a metal halide salt reaction product to accelerate the formation of the metal halide salt without its substantial removal from the substrate. The metal halide salt is removed from the substrate by contact of the substrate with a solvent for the metal halide salt.
摘要翻译： 公开了一种金属化（例如铜）衬底的辐射诱导干蚀刻的方法，其中衬底被图案化地暴露于与衬底反应以形成金属卤化物盐反应产物的卤素气体气氛中的激光束 以加速金属卤化物盐的形成，而不将其从基材中大量除去。 金属卤化物盐通过与底物与金属卤化物盐的溶剂的接触从基材中除去。
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5.发明授权Circuit design verification tool and method therefor using maxwell's equations 失效电路设计验证工具及其使用Maxwell方程的方法
公开(公告)号：US6106567A
公开(公告)日：2000-08-22
申请号：US69028
申请日：1998-04-28
申请人： Warren D. Grobman , Mark H. Nodine
发明人： Warren D. Grobman , Mark H. Nodine
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： Very high speed circuits are adversely effected by parasitic capacitances and line resistances. At high speeds these values of capacitance and resistance change with frequency. A method of verification of the design of high speed circuits includes a simulation of the effects of these changes in resistance and capacitance which occur at high frequency. There is a logic component and a physical-layout component which are combined to provide a full simulation of the circuit taking into account these effects which occur at very high frequency. The physical-layout component utilizes Maxwell's equations in their entirety without removing the time dependent effects. One embodiment considers only cases defined by the bus protocol, reducing the computational penalty of complete electromagnetic simulation.
摘要翻译： 非常高速的电路受到寄生电容和线路电阻的不利影响。 在高速下，这些电容值和电阻值随频率而变化。 验证高速电路设计的方法包括在高频下发生的这些电阻和电容变化的影响的模拟。 存在逻辑组件和物理布局组件，其被组合以提供考虑到以非常高的频率发生的这些效应的电路的完全模拟。 物理布局组件全部使用麦克斯韦方程，而不会消除时间依赖性影响。 一个实施例仅考虑由总线协议定义的情况，从而降低完整电磁仿真的计算量。
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公开(公告)号：US5060116A
公开(公告)日：1991-10-22
申请号：US513342
申请日：1990-04-20
申请人： Warren D. Grobman , Charles J. Kraus, deceased , by Paula A. Kraus, executrix , Leon L. Wu , Herbert I. Stoller
发明人： Warren D. Grobman , Charles J. Kraus, deceased , by Paula A. Kraus, executrix , Leon L. Wu , Herbert I. Stoller
IPC分类号： H01L23/538
CPC分类号： H01L23/5382 , H01L2924/0002 , Y10T29/49156
摘要： A electronics system and method are provided which allow engineering changes to be made to a substrate without requiring the addition of fly wires and without requiring relatively large areas of pads for attaching these wires. Each device site is surrounded by a series of engineering change ring patterns. A series of engineering change patterns allow change interconnections between device sites to be made. Fan-in metallizations extend inwardly to the device sites from these change patterns, with a series of vias making surface connections adjacent to the ring patterns. Fan-out metallizations extend from the device site pads to the ring patterns, with a series of vias making surface connections adjacent to the ring patterns. Engineering changes are made by directly writing surface metal deposits to make the appropriate connections between the vias and the ring pattern. The original chip pad connections and the new ring pattern connections can be appropriately isolated by laser deletions, if necessary.
摘要翻译： 提供了一种电子系统和方法，其允许对基板进行工程改变，而不需要添加飞线，并且不需要相对较大的用于附接这些线的焊盘区域。 每个设备站点都被一系列工程变更环形图案包围。 一系列工程变更模式允许在设备站点之间进行更改互连。 扇形金属化从这些变化图案向内延伸到器件位置，其中一系列通孔使表面连接邻近环形图案。 扇出金属化从器件现场焊盘延伸到环形图案，一系列通孔使表面连接与环形图案相邻。 通过直接写入表面金属沉积物以形成通孔和环形图案之间的适当连接来进行工程变更。 如果需要，原始芯片焊盘连接和新的环形图案连接可以通过激光缺陷进行适当的隔离。
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7.发明授权公开(公告)号：US06645678B2
公开(公告)日：2003-11-11
申请号：US09727666
申请日：2000-12-01
IPC分类号： G03F900
CPC分类号： G03F7/70466 , G03F1/30 , G03F7/70566
摘要： A method and apparatus for making an integrated circuit takes advantage of both polarized and phase shifted light in order to achieve a fine feature. The feature on the integrated circuit is obtained by exposing a first region to light that has a first polarization state, exposing a second portion of the wafer to polarized light in the first polarization state but which is also phase shifted about 180 degrees. A region between the first and second region may be unexposed to light. The region between the first and the second region is the position of the fine feature. In areas where the first region and the second region need to be joined together but no feature is intended to be formed, there is a third region between the first and second regions which is exposed to polarized light that has a second polarization state which is orthogonal to that of the polarized light which exposes the first and second regions. The result is that the boundary between either the first or second region and the third region is fully exposed. Thus there is no artifact or extra feature formed in this boundary area between the first and second regions. Masks are made with corresponding regions to the first, second, and third regions so that the light in these polarized and phase shifted states is properly provided to the integrated circuit.
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公开(公告)号：US4880684A
公开(公告)日：1989-11-14
申请号：US167290
申请日：1988-03-11
申请人： David W. Boss , Timothy W. Carr , Derry J. Dubetsky , George M. Greenstein , Warren D. Grobman , Carl P. Hayunga , Amanda H. Kumar , Walter F. Lange , Robert H. Massey , Paul H. Palmateer , John A. Romano , Da-Yuan Shih
发明人： David W. Boss , Timothy W. Carr , Derry J. Dubetsky , George M. Greenstein , Warren D. Grobman , Carl P. Hayunga , Amanda H. Kumar , Walter F. Lange , Robert H. Massey , Paul H. Palmateer , John A. Romano , Da-Yuan Shih
IPC分类号： H05K9/00 , H01L23/498 , H05K3/46
CPC分类号： H01L23/49827 , H01L2924/0002 , H01L2924/09701 , H01L2924/15312 , Y10S428/901 , Y10T29/49155 , Y10T29/49163 , Y10T29/49165 , Y10T428/12396 , Y10T428/24917 , Y10T428/24926 , Y10T428/31681
摘要： Sealing and stress relief are provided to a low-fracture strength glass-ceramic substrate. Hermeticity is addressed through the use of capture pads in alignment with vias and through polymer overlays with interconnection between the underlying via or pad metallurgy and the device, chip, wire or pin bonded to the surface of the layer. Multilevel structures are taught along with a self-aligned sealing and wiring process.
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公开(公告)号：US4405238A
公开(公告)日：1983-09-20
申请号：US265140
申请日：1981-05-20
CPC分类号： G03F9/7076 , G02B5/1876 , G03F9/7049
摘要： Fine alignment of mask and wafer, using Fresnel zone plates is achieved. Light is focused on the wafer by a zone plate in the mask. Light diffracted from a zone plate on the wafer is received by a sensor. The received light is coded (analog or digital) to indicate alignment. For analog coding the wafer zone plate diffracts light to the sensor from an area of the wafer zone plate which is indicative of alignment. For digital coding, the wafer zone plate is digitally encoded as a function of alignment to similarly code the diffracted light. To eliminate ambiguity, the mask zone plate is formed from a plurality of "elements", each of which is itself a Fresnel zone plate. The focal length of the elemental Fresnel zone plate can be related to the mask/wafer separation distance, whereas the focal length of the macro zone plate (made up of a plurality of the elemental zone plates) is related to the distance between mask and light sensor.
摘要翻译： 实现了使用菲涅耳带片的掩模和晶片的精细对准。 光通过掩模中的区域板聚焦在晶片上。 从晶片上的区域板衍射的光由传感器接收。 接收的光被编码（模拟或数字）以指示对准。 对于模拟编码，晶片区域板从指示对准的晶片区域板的区域将光衍射到传感器。 对于数字编码，晶片区域板作为对准的函数进行数字编码，以类似地对衍射光进行编码。 为了消除歧义，掩模区域板由多个“元件”形成，其中每个“元件”本身都是菲涅尔区域板。 元素菲涅耳带片的焦距可以与掩模/晶片间隔距离相关，而宏观区域板（由多个元素区域板组成）的焦距与掩模和光线之间的距离有关 传感器。
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公开(公告)号：US4453086A
公开(公告)日：1984-06-05
申请号：US336465
申请日：1981-12-31
申请人： Warren D. Grobman
发明人： Warren D. Grobman
IPC分类号： H01L21/66 , G01N23/18 , G01N23/203 , G03F1/40 , G03F1/86 , H01L21/027 , C08J7/10
CPC分类号： G03F1/86 , G01N23/18 , G01N23/203 , G03F1/40
摘要： In electron beam testing systems wherein high energy, high resolution electron beams are used to test lithographic masks, a technique and apparatus are described for discharging electrons which are left on the surface of the mask, and which alter the input trajectory of the electron beam. The materials used in these masks are such that induced photoconductivity and photoemissivity are extremely low and are incapable of providing sufficient electron discharge. A thin, low work function coating is applied over the entire mask surface, the coating being transparent to the radiation which will later be incident upon the mask when it is used in a fabrication process. Due to induced photoemission in the thin coating layer, enough photoemitted electrons will be produced to balance the buildup of electrons from the electron beam, thereby discharging the surface of the mask. The electron beam is a high energy beam, having energies greater than about 5000 eV, and a resolution less than about 1 micrometer.
摘要翻译： 在其中使用高能量，高分辨率电子束来测试光刻掩模的电子束测试系统中，描述了放置在掩模表面上并且改变电子束的输入轨迹的电子的技术和装置。 这些掩模中使用的材料使得感应的光电导率和光电散率极低，并且不能提供足够的电子放电。 在整个掩模表面上施加薄的低功函数涂层，所述涂层对于在制造过程中使用时将随后入射到掩模上的辐射是透明的。 由于在薄涂层中的诱导光电子发射，将产生足够的光电子以平衡来自电子束的电子的积累，从而排出掩模的表面。 电子束是能量大于约5000eV的能量束，分辨率小于约1微米。
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