利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

9 条记录 (耗时 0.025 秒)

    Rasterizer for a pattern generation apparatus
    3.
    发明授权
    Rasterizer for a pattern generation apparatus 失效
    光栅化器用于图案生成装置

    公开(公告)号：US5533170A

    公开(公告)日：1996-07-02

    申请号：US344417

    申请日：1994-11-22

    申请人： Robin L. Teitzel ,  Matthew J. Jolley ,  James B. Campbell ,  Richard K. George ,  John Wipfli

    发明人： Robin L. Teitzel ,  Matthew J. Jolley ,  James B. Campbell ,  Richard K. George ,  John Wipfli

    IPC分类号： G03F1/08 ,  G03F7/20 ,  G06T11/20 ,  H01L21/027 ,  G06K15/00

    CPC分类号： G03F7/704 ,  G03F7/70508 ,  G06T11/203

    摘要： A rasterizer for generating pixel values for a pattern generation apparatus. The pixel values drive the printing mechanism of the pattern generation apparatus. The rasterizer receives a file defining the pattern to be printed, fractures the pattern into sub frames, rasterizes each sub frame and then coordinates the provision of the shaded pixel values to the pattern generation apparatus. The rasterizer of the present invention is comprised primarily of a host processing means for fracturing and translating the file into one or more sub frames of pixels; geometry engines for rasterizing each sub frame; beam boards for providing the pixel shading values to a pattern generation system; a serial bus for coupling the host processor means to the geometry engines and beam boards and a pixel bus for coupling each of the geometry engines to each of the beam boards.

    摘要翻译： 一种用于生成图案生成装置的像素值的光栅化器。 像素值驱动图案生成装置的打印机构。 光栅化器接收定义要打印的图案的文件，将图案断裂成子帧，对每个子帧进行光栅化，然后协调向图案生成装置提供阴影像素值。 本发明的光栅化器主要包括用于将文件压缩并转换成一个或多个像素子帧的主机处理装置; 用于光栅化每个子帧的几何引擎; 光束板，用于将像素着色值提供给图案生成系统; 用于将主处理器装置耦合到几何引擎和波束板的串行总线和用于将每个几何引擎耦合到每个波束板的像素总线。

    Retargetable buffer probe
    6.
    发明授权
    Retargetable buffer probe 失效
    可重定位缓冲探针

    公开(公告)号：US4701696A

    公开(公告)日：1987-10-20

    申请号：US801450

    申请日：1985-11-25

    申请人： David W. Bogardus ,  Robin L. Teitzel ,  David D. Chapman

    发明人： David W. Bogardus ,  Robin L. Teitzel ,  David D. Chapman

    IPC分类号： G01R31/26 ,  G01R1/073 ,  G01R31/28 ,  G01R31/3185 ,  G06F11/25 ,  G01R31/02

    CPC分类号： G01R1/073 ,  G06F11/25

    摘要： A probe for a logic analyzer includes a replacement plug assembly comprising those portions of probe equipment which must be specifically adapted to accommodate a selected microprocessor, and a buffer probe assembly comprising those portions of probe equipment which are adapted for use with a wide variety of microprocessors. The replacement plug assembly and the buffer probe assembly are mechanically joined and electrically coupled by a square pin connector so that the replacement plug assembly may be removed from the probe and replaced with a differently configured replacement plug assembly when a different microprocessor is to be probed. Thus only a portion of the probe is changed to retarget the probe for different microprocessors. Each replacement plug assembly cross-connects data, address, and control lines of the associated microprocessor to the same corresponding groups of data, address, and control signal input channels of the buffer probe assembly as every other replacement plug assembly so that the data, address, and control information is transmitted to the data acquisition system through the buffer probe assembly over the same input line groups regardless of the microprocessor under test. This enables programmable data acquisition circuits of the logic analyzer to accommodate microprocessors having differing pin arrangements without a change in data acquisition circuit hardware or wiring.

    摘要翻译： 用于逻辑分析仪的探针包括替换插头组件，其包括必须特别适于容纳所选择的微处理器的探针设备的那些部分，以及包括适于与各种微处理器一起使用的探针设备的那些部分的缓冲探针组件 。 更换插头组件和缓冲探针组件通过方形销连接器机械连接和电耦合，使得替换插头组件可以从探头移除并且当不同的微处理器被探测时被替换为不同配置的替换插头组件。 因此，只有一部分探针被改变以重新定位不同微处理器的探头。 每个替代插头组件将相关微处理器的数据，地址和控制线交叉连接到缓冲探针组件的相同对应组的数据，地址和控制信号输入通道，作为每个其他替换插头组件，使得数据，地址 ，并且通过相同的输入线组上的缓冲探针组件将控制信息发送到数据采集系统，而与被测微处理器无关。 这使得逻辑分析器的可编程数据采集电路适应具有不同引脚布置的微处理器，而不改变数据采集电路硬件或布线。

    Variable tracking word recognizer for detecting the occurrence of a dynamic-variable address
    7.
    发明授权
    Variable tracking word recognizer for detecting the occurrence of a dynamic-variable address 失效
    可变跟踪字识别器，用于检测动态变量地址的发生

    公开(公告)号：US4748556A

    公开(公告)日：1988-05-31

    申请号：US737760

    申请日：1985-05-28

    申请人： Gerd H. Hoeren ,  David D. Chapman ,  Robin L. Teitzel ,  Steven R. Palmquist

    发明人： Gerd H. Hoeren ,  David D. Chapman ,  Robin L. Teitzel ,  Steven R. Palmquist

    IPC分类号： G06F11/28 ,  G06F11/25 ,  G06F11/30 ,  G06F11/34 ,  G06F11/36

    CPC分类号： G06F11/3636 ,  G06F11/25 ,  G06F11/34

    摘要： A variable tracking word recognizer generates an indicating signal when a microprocessor has accessed a memory stack location storing a dynamically addressed variable, the address of the variable being the sum of a dynamically assigned base address of the memory stack and a known address offset where the variable is stored on the stack in relation to the base address. The variable tracking word recognizer stores the dynamically assigned base address, when determined by a space allocation subroutine of a program running on the microprocessor, and then monitors the addresses subsequently appearing on the microprocessor address bus, generating the indicating signal when the current address matches the combination of stored base address and known address offset. The variable tracking word recognizer comprises circuitry to generate a storage control signal when the base address appears on the data bus of the microprocessor, a base register for storing the base address on occurrence of the storage control signal, an arithmetic logic unit for determining the difference between the number stored in the base register and each address appearing on the microprocessor address bus, and a conventional word recognizer to generate the indicating signal when the difference so generated equals the known offset.

    摘要翻译： 当微处理器访问存储动态寻址的变量的存储器堆栈位置时，可变跟踪字识别器产生指示信号，变量的地址是存储器堆栈的动态分配的基地址和已知的地址偏移的和，其中变量 相对于基地址存储在堆栈上。 当由微处理器上运行的程序的空间分配子程序确定时，可变跟踪字识别器存储动态分配的基地址，然后监视随后出现在微处理器地址总线上的地址，当当前地址匹配时产生指示信号 存储基地址和已知地址偏移量的组合。 可变跟踪字识别器包括当基地址出现在微处理器的数据总线上时产生存储控制信号的电路，存储控制信号出现时用于存储基地址的基址寄存器，用于确定差分的算术逻辑单元 存储在基本寄存器中的数字和出现在微处理器地址总线上的每个地址之间，以及传统的字识别器，当所生成的差值等于已知的偏移量时，产生指示信号。