公开(公告)号：US07166524B2

公开(公告)日：2007-01-23

申请号：US11003000

申请日：2004-12-01

申请人： Amir Al-Bayati ,  Rick J. Roberts ,  Kenneth S. Collins ,  Ken MacWilliams ,  Hiroji Hanawa ,  Kartik Ramaswamy ,  Biagio Gallo ,  Andrew Nguyen

发明人： Amir Al-Bayati ,  Rick J. Roberts ,  Kenneth S. Collins ,  Ken MacWilliams ,  Hiroji Hanawa ,  Kartik Ramaswamy ,  Biagio Gallo ,  Andrew Nguyen

IPC分类号： H01L21/425

CPC分类号： H01J37/32082 ,  H01J37/321 ,  H01L21/76254

摘要： An integrated microelectronic circuit has a multi-layer interconnect structure overlying the transistors consisting of stacked metal pattern layers and insulating layers separating adjacent ones of said metal pattern layers. Each of the insulating layers is a dielectric material with plural gas bubbles distributed within the volume of the dielectric material to reduce the dielectric constant of the material, the gas bubbles being formed by ion implantation of a gaseous species into the dielectric material.

摘要翻译： 集成的微电子电路具有覆盖由堆叠的金属图案层和分离相邻的所述金属图案层的绝缘层的晶体管的多层互连结构。 每个绝缘层是具有分布在电介质材料的体积内的多个气泡的介电材料，以降低材料的介电常数，气泡通过将气态物质离子注入电介质材料而形成。

公开(公告)号：US20050191828A1

公开(公告)日：2005-09-01

申请号：US11003000

申请日：2004-12-01

申请人： Amir Al-Bayati ,  Rick Roberts ,  Kenneth Collins ,  Ken MacWilliams ,  Hiroji Hanawa ,  Kartik Ramaswamy ,  Biagio Gallo ,  Andrew Nguyen

发明人： Amir Al-Bayati ,  Rick Roberts ,  Kenneth Collins ,  Ken MacWilliams ,  Hiroji Hanawa ,  Kartik Ramaswamy ,  Biagio Gallo ,  Andrew Nguyen

IPC分类号： H01J37/32 ,  H01L21/4763

CPC分类号： H01J37/32082 ,  H01J37/321 ,  H01L21/76254

摘要： An integrated microelectronic circuit has a multi-layer interconnect structure overlying the transistors consisting of stacked metal pattern layers and insulating layers separating adjacent ones of said metal pattern layers. Each of the insulating layers is a dielectric material with plural gas bubbles distributed within the volume of the dielectric material to reduce the dielectric constant of the material, the gas bubbles being formed by ion implantation of a gaseous species into the dielectric material.

摘要翻译： 集成的微电子电路具有覆盖由堆叠的金属图案层和分离相邻的所述金属图案层的绝缘层的晶体管的多层互连结构。 每个绝缘层是具有分布在电介质材料的体积内的多个气泡的介电材料，以降低材料的介电常数，气泡通过将气态物质离子注入电介质材料而形成。

公开(公告)号：US20070042580A1

公开(公告)日：2007-02-22

申请号：US11551196

申请日：2006-10-19

申请人： Amir Al-Bayati ,  Rick Roberts ,  Kenneth Collins ,  Ken MacWilliams ,  Hiroji Hanawa ,  Kartik Ramaswamy ,  Biagio Gallo ,  Andrew Nguyen

发明人： Amir Al-Bayati ,  Rick Roberts ,  Kenneth Collins ,  Ken MacWilliams ,  Hiroji Hanawa ,  Kartik Ramaswamy ,  Biagio Gallo ,  Andrew Nguyen

IPC分类号： H01L21/425

CPC分类号： H01L21/823864 ,  C23C16/56 ,  H01L21/02126 ,  H01L21/02203 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/02321 ,  H01L21/0234 ,  H01L21/31695 ,  H01L21/7682 ,  H01L21/76825 ,  H01L21/823871 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2221/1047 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： An integrated microelectronic circuit has a multi-layer interconnect structure overlying the transistors consisting of stacked metal pattern layers and insulating layers separating adjacent ones of said metal pattern layers. Each of the insulating layers is a dielectric material with plural gas bubbles distributed within the volume of the dielectric material to reduce the dielectric constant of the material, the gas bubbles being formed by ion implantation of a gaseous species into the dielectric material.

摘要翻译： 集成的微电子电路具有覆盖由堆叠的金属图案层和分离相邻的所述金属图案层的绝缘层的晶体管的多层互连结构。 每个绝缘层是具有分布在电介质材料的体积内的多个气泡的介电材料，以降低材料的介电常数，气泡通过将气态物质离子注入电介质材料而形成。

公开(公告)号：US07642180B2

公开(公告)日：2010-01-05

申请号：US11901969

申请日：2007-09-18

申请人： Amir Al-Bayati ,  Kenneth S. Collins ,  Hiroji Hanawa ,  Kartik Ramaswamy ,  Biagio Gallo ,  Andrew Nguyen

发明人： Amir Al-Bayati ,  Kenneth S. Collins ,  Hiroji Hanawa ,  Kartik Ramaswamy ,  Biagio Gallo ,  Andrew Nguyen

IPC分类号： H01L21/44

CPC分类号： H01J37/321 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/7843 ,  H01L29/785 ,  H01L29/78618

摘要： A process for conformally doping through the vertical and horizontal surfaces of a 3-dimensional vertical transistor in a semiconductor-on-insulator structure employs an RF oscillating torroidal plasma current to perform either conformal ion implantation, or conformal deposition of a dopant-containing film which can then be heated to drive the dopants into the transistor. Some embodiments employ both conformal ion implantation and conformal deposition of dopant containing films, and in those embodiments in which the dopant containing film is a pure dopant, the ion implantation and film deposition can be performed simultaneously.

摘要翻译： 通过绝缘体上半导体结构中的三维垂直晶体管的垂直和水平表面进行保形掺杂的工艺采用RF振荡环形等离子体电流来执行保形离子注入或含掺杂剂膜的共形沉积 然后可以加热以将掺杂剂驱动到晶体管中。 一些实施例采用包含掺杂剂的膜的共形离子注入和共形沉积，并且在其中含掺杂剂的膜是纯掺杂剂的那些实施例中，可以同时执行离子注入和膜沉积。

公开(公告)号：US07320734B2

公开(公告)日：2008-01-22

申请号：US10646527

申请日：2003-08-22

申请人： Kenneth S. Collins ,  Hiroji Hanawa ,  Kartik Ramaswamy ,  Andrew Nguyen ,  Amir Al-Bayati ,  Biagio Gallo ,  Gonzalo Antonio Monroy

发明人： Kenneth S. Collins ,  Hiroji Hanawa ,  Kartik Ramaswamy ,  Andrew Nguyen ,  Amir Al-Bayati ,  Biagio Gallo ,  Gonzalo Antonio Monroy

IPC分类号： C23C16/00 ,  C23F1/00

CPC分类号： H01J37/32082 ,  H01J37/321

摘要： A system for processing a workpiece includes a plasma immersion ion implantation reactor with an enclosure having a side wall and a ceiling and defining a chamber, and a workpiece support pedestal within the chamber having a workpiece support surface facing the ceiling and defining a process region extending generally across the wafer support pedestal and confined laterally by the side wall and axially between the workpiece support pedestal and the ceiling. The enclosure has at least a first pair of openings at generally opposite sides of the process region, and a first hollow conduit outside the chamber having first and second ends connected to respective ones of the first pair of openings, so as to provide a first reentrant path extending through the conduit and across the process region. The reactor further includes a gas distribution apparatus on or near an interior surface of the reactor for introducing a process gas containing a first species to be ion implanted into a surface layer of the workpiece, and a first RF plasma source power applicator for generating a plasma in the chamber. The system further includes a second wafer processing apparatus and a wafer transfer apparatus for transferring the workpiece between the plasma immersion implantation rector and the second wafer processing apparatus.

摘要翻译： 一种用于处理工件的系统包括具有外壳的等离子体浸入式离子注入反应器，所述外壳具有侧壁和天花板并且限定室，并且所述室内的工件支撑基座具有面向天花板的工件支撑表面，并且限定延伸 通常横跨晶片支撑台座并且由侧壁横向限制并且轴向地在工件支撑台座和天花板之间。 外壳在工艺区域的大致相对侧具有至少第一对开口，腔室外的第一中空导管具有连接到第一对开口中的相应开口的第一端和第二端，以便提供第一凹槽 路径延伸穿过管道并跨越过程区域。 反应器还包括在反应器的内表面上或附近的气体分配装置，用于将含有待离子注入的第一种类的工艺气体引入到工件的表面层中;以及第一RF等离子体源功率施加器，用于产生等离子体 在房间里 该系统还包括第二晶片处理装置和晶片传送装置，用于在等离子浸入植入装置和第二晶片处理装置之间传送工件。

公开(公告)号：US07312148B2

公开(公告)日：2007-12-25

申请号：US11199570

申请日：2005-08-08

申请人： Kartik Ramaswamy ,  Hiroji Hanawa ,  Biagio Gallo ,  Kenneth S Collins ,  Kai Ma ,  Vijay Parihar ,  Dean Jennings ,  Abhilash J. Mayur ,  Amir Al-Bayati ,  Andrew Nguyen

发明人： Kartik Ramaswamy ,  Hiroji Hanawa ,  Biagio Gallo ,  Kenneth S Collins ,  Kai Ma ,  Vijay Parihar ,  Dean Jennings ,  Abhilash J. Mayur ,  Amir Al-Bayati ,  Andrew Nguyen

IPC分类号： H01L21/44

CPC分类号： H01L21/76877 ,  H01L21/76843 ,  H01L21/76864 ,  H01L21/76873

摘要： A method of forming a barrier layer for a thin film structure on a semiconductor substrate includes forming high aspect ratio openings in a base layer having vertical side walls, depositing a dielectric barrier layer comprising a dielectric compound of a barrier metal on the surfaces of the high aspect ratio openings including the vertical side walls and depositing a metal barrier layer comprising the barrier metal on the first barrier layer. The method further includes reflowing the metal barrier layer by (a) directing light from an array of continuous wave lasers into a line of light extending at least partially across the thin film structure, and (b) translating the line of light relative to the thin film structure in a direction transverse to the line of light.

摘要翻译： 在半导体衬底上形成用于薄膜结构的阻挡层的方法包括在具有垂直侧壁的基底层中形成高纵横比的开口，在高的表面上沉积包含阻挡金属的电介质化合物的介电阻挡层 纵横比开口，包括垂直侧壁，并且在第一阻挡层上沉积包含阻挡金属的金属阻挡层。 该方法还包括通过（a）将来自连续波激光阵列的光引导到至少部分穿过薄膜结构延伸的光线中来回流金属阻挡层，以及（b）相对于薄的平移光线 薄膜结构在横向于光线的方向上。

公开(公告)号：US07292428B2

公开(公告)日：2007-11-06

申请号：US11115951

申请日：2005-04-26

申请人： Hiroji Hanawa ,  Andrew Nguyen ,  Kenneth S. Collins ,  Kartik Ramaswamy ,  Biagio Gallo ,  Amir Al-Bayati

发明人： Hiroji Hanawa ,  Andrew Nguyen ,  Kenneth S. Collins ,  Kartik Ramaswamy ,  Biagio Gallo ,  Amir Al-Bayati

IPC分类号： H02N13/00

CPC分类号： H01L21/68742 ,  H01L21/6831

摘要： A lift pin assembly for use in a reactor for processing a workpiece includes plural lift pins extending generally parallel with a lift direction, each of the plural lift pins having a top end for supporting a workpiece and a bottom end. A lift table faces the bottom ends of the pins and is translatable in a direction generally parallel with the lift direction. A small force detector senses a force exerted by the lift pins that is sufficiently large to indicate a chucked wafer and sufficiently small to avoid dechucking a wafer. A large force detector senses a force exerted by the lift pins in a range sufficient to de-chuck the wafer.

摘要翻译： 用于处理工件的反应器中的提升销组件包括大体平行于提升方向延伸的多个提升销，多个提升销中的每一个具有用于支撑工件的顶端和底端。 升降台面向销的底端，并可在与升降方向大致平行的方向上平移。 小的力检测器感测由提升销施加的足够大的力以指示夹紧的晶片并且足够小以避免使晶片脱扣。 大的力检测器感测由提升销施加的力在足以脱离晶片的范围内。

公开(公告)号：US07109098B1

公开(公告)日：2006-09-19

申请号：US11131904

申请日：2005-05-17

申请人： Kartik Ramaswamy ,  Hiroji Hanawa ,  Biagio Gallo ,  Kenneth S. Collins ,  Kai Ma ,  Vijay Parihar ,  Dean Jennings ,  Abhilash J. Mayur ,  Amir Al-Bayati ,  Andrew Nguyen

发明人： Kartik Ramaswamy ,  Hiroji Hanawa ,  Biagio Gallo ,  Kenneth S. Collins ,  Kai Ma ,  Vijay Parihar ,  Dean Jennings ,  Abhilash J. Mayur ,  Amir Al-Bayati ,  Andrew Nguyen

IPC分类号： H01L21/26

CPC分类号： H01L21/268 ,  H01L21/02118 ,  H01L21/0212 ,  H01L21/02274 ,  H01L21/02321 ,  H01L21/26513 ,  H01L21/3127 ,  H01L21/314 ,  H01L21/3146

摘要： A method of forming semiconductor junctions in a semiconductor material of a workpiece includes ion implanting dopant impurities in selected regions of the semiconductor material, introducing an optical absorber material precursor gas into a chamber containing the workpiece, generating an RF oscillating toroidal plasma current in a reentrant path that includes a process zone overlying the workpiece by applying RF source power, so as to deposit a layer of an optical absorber material on the workpiece, and optically annealing the workpiece so as to activate dopant impurities in the semiconductor material.

摘要翻译： 在工件的半导体材料中形成半导体结的方法包括在半导体材料的选定区域中的离子注入掺杂剂杂质，将光吸收材料前体气体引入到包含工件的腔室中，在折返中产生RF振荡环形等离子体电流 路径，其包括通过施加RF源功率覆盖工件的工艺区域，以便在工件上沉积光吸收材料层，并对工件进行光学退火，以激活半导体材料中的掺杂剂杂质。

公开(公告)号：US07037813B2

公开(公告)日：2006-05-02

申请号：US10646612

申请日：2003-08-22

申请人： Kenneth S. Collins ,  Hiroji Hanawa ,  Kartik Ramaswamy ,  Andrew Nguyen ,  Amir Al-Bayati ,  Biagio Gallo ,  Gonzalo Antonio Monroy

发明人： Kenneth S. Collins ,  Hiroji Hanawa ,  Kartik Ramaswamy ,  Andrew Nguyen ,  Amir Al-Bayati ,  Biagio Gallo ,  Gonzalo Antonio Monroy

IPC分类号： H01L21/04 ,  H01L21/84

CPC分类号： H01J37/32357 ,  H01J37/32082 ,  H01J37/321 ,  H01J37/32412 ,  H01L21/2236

摘要： A method for implanting ions in a surface layer of a workpiece includes placing the workpiece on a workpiece support in a chamber with the surface layer being in facing relationship with a ceiling of the chamber, thereby defining a processing zone between the workpiece and the ceiling, and introducing into the chamber a process gas including the species to be implanted in the surface layer of the workpiece. The method includes generating from the process gas a plasma by capacitively coupling RF source power across the workpiece support and the ceiling or the sidewall from an RF source power generator. The method further includes applying an RF bias from an RF bias generator to the workpiece support.

摘要翻译： 用于将离子注入工件的表面层的方法包括将工件放置在腔室中的工件支撑件上，其中表面层与腔室的天花板处于面对关系，从而在工件和天花板之间限定加工区域， 并且将包括待植入物种的工艺气体引入到工件的表面层中。 该方法包括通过从RF源功率发生器电容耦合RF源功率跨过工件支撑件和天花板或侧壁来从工艺气体产生等离子体。 该方法还包括将来自RF偏置发生器的RF偏压施加到工件支撑件。

公开(公告)号：US07465478B2

公开(公告)日：2008-12-16

申请号：US11046660

申请日：2005-01-28

申请人： Kenneth S. Collins ,  Hiroji Hanawa ,  Kartik Ramaswamy ,  Andrew Nguyen ,  Amir Al-Bayati ,  Biagio Gallo

发明人： Kenneth S. Collins ,  Hiroji Hanawa ,  Kartik Ramaswamy ,  Andrew Nguyen ,  Amir Al-Bayati ,  Biagio Gallo

IPC分类号： C23C14/48 ,  B05D3/06 ,  H05H1/24 ,  H05H1/46 ,  H05H1/02

CPC分类号： H01J37/321 ,  H01J37/32082 ,  Y10S438/906

摘要： A method of processing a workpiece includes placing the workpiece on a workpiece support pedestal in a main chamber with a gas distribution showerhead, introducing a process gas into a remote plasma source chamber and generating a plasma in the remote plasma source chamber, transporting plasma-generated species from the remote plasma source chamber to the gas distribution showerhead so as to distribute the plasma-generated species into the main chamber through the gas distribution showerhead, and applying plasma RF power into the main chamber.

摘要翻译： 一种处理工件的方法包括将工件放置在具有气体分配喷头的主室中的工件支撑基座上，将工艺气体引入远程等离子体源室并在远程等离子体源室中产生等离子体，传输等离子体产生的 从远程等离子体源室到气体分配淋浴喷头的物质，以便通过气体分配喷头将等离子体产生的物质分配到主室中，并将等离子体RF功率施加到主室中。