公开(公告)号：US20170063382A1

公开(公告)日：2017-03-02

申请号：US14835656

申请日：2015-08-25

Applicant: Amit Kumar Srivastava

Inventor： Amit Kumar Srivastava

IPC: H03L7/07 ,  H03L7/095 ,  H03L7/091

CPC classification number: H03L7/087 ,  H03L7/1976 ,  H03L7/23 ,  H03L7/235 ,  H03M1/50

Abstract: Described is an apparatus which comprises: a first clocking source having a first divider; a second clocking source having a second divider, wherein the first and second clocking sources are inductively coupled; and calibration logic to monitor clock signals associated with the first and second clocking sources and to generate at least one calibration code for adjusting at least one divider ratio of the first or second dividers according to the monitored clock signals.

Abstract translation: 描述了一种装置，包括：具有第一分频器的第一时钟源; 具有第二分频器的第二时钟源，其中所述第一和第二时钟源被感应耦合; 以及校准逻辑，用于监视与第一和第二时钟源相关联的时钟信号，并产生至少一个校准代码，用于根据所监视的时钟信号调整第一或第二分频器的至少一个分频比。

公开(公告)号：US20190138479A1

公开(公告)日：2019-05-09

申请号：US16236471

申请日：2018-12-29

Applicant: Amit Kumar Srivastava ,  Asad Azam

Inventor： Amit Kumar Srivastava ,  Asad Azam

IPC: G06F13/40 ,  G06F13/16

Abstract: An integrated circuit for monitoring components of the integrated circuit, comprising: a resource monitoring circuit configured to: track activity factors for a plurality of components of the integrated circuit; evaluate the activity factors for each of the plurality of components; determine whether an activity factor for a particular component of the plurality of components exceeds a threshold; and transmit, from the resource monitoring circuit, a signal to a software element, causing the software element to deactivate the particular component and activate an alternate component, when the activity factor for the particular component exceeds the threshold and the alternate component is available to substitute for the particular component.

公开(公告)号：US20190004991A1

公开(公告)日：2019-01-03

申请号：US15635299

申请日：2017-06-28

Applicant: Kenneth P. Foust ,  Amit Kumar Srivastava ,  Nobuyuki Suzuki

Inventor： Kenneth P. Foust ,  Amit Kumar Srivastava ,  Nobuyuki Suzuki

IPC: G06F13/42 ,  G06F13/364 ,  G06F13/24

Abstract: In an embodiment, a host controller includes a clock control circuit to cause the host controller to communicate a clock signal on a clock line of an interconnect, the clock control circuit to receive an indication that a first device is to send information to the host controller and to dynamically release control of the clock line of the interconnect to enable the first device to drive a second clock signal onto the clock line of the interconnect for communication with the information. Other embodiments are described and claimed.

公开(公告)号：US07498848B2

公开(公告)日：2009-03-03

申请号：US11851380

申请日：2007-09-06

Applicant: Sanjay Kumar Wadhwa ,  Amit Kumar Srivastava

Inventor： Sanjay Kumar Wadhwa ,  Amit Kumar Srivastava

IPC: H03K5/19

CPC classification number: H03K5/19 ,  G01R31/31725 ,  G01R31/31727 ,  H03K5/26

Abstract: A clock monitor system for monitoring an input clock signal in an integrated circuit (IC) includes a clock failure detection circuit and a delay circuit. The clock failure detection circuit generates a control signal based on the input clock signal. The delay circuit is connected to the clock failure detection circuit and provides a clock status signal based on the control signal. The clock status signal indicates whether the input clock signal is operating correctly. The delay circuit provides the clock status signal to the IC after a predetermined number of input clock cycles.

Abstract translation: 用于监视集成电路（IC）中的输入时钟信号的时钟监视器系统包括时钟故障检测电路和延迟电路。 时钟故障检测电路基于输入时钟信号产生控制信号。 延迟电路连接到时钟故障检测电路，并根据控制信号提供时钟状态信号。 时钟状态信号指示输入时钟信号是否正常工作。 延迟电路在预定数量的输入时钟周期之后向IC提供时钟状态信号。

公开(公告)号：US20210318981A1

公开(公告)日：2021-10-14

申请号：US17358363

申请日：2021-06-25

Applicant: Janusz Jurski ,  Amit Kumar Srivastava ,  Matthew A. Schnoor ,  Myron Loewen ,  Tim McKee

Inventor： Janusz Jurski ,  Amit Kumar Srivastava ,  Matthew A. Schnoor ,  Myron Loewen ,  Tim McKee

IPC: G06F13/42 ,  G06F13/40

Abstract: An apparatus may include a controller for a system management bus. The controller may be to: detect a trigger event associated with the system management bus; in response to a detection of the trigger event, transmit a broadcast address on the system management bus, where the broadcast address is not used in a first communication protocol; and in response to a determination that the transmitted broadcast address was acknowledged, use a second communication protocol for transmissions on the system management bus. Other embodiments are described and claimed.

公开(公告)号：US10915415B2

公开(公告)日：2021-02-09

申请号：US15776384

申请日：2016-10-13

Applicant: INTEL CORPORATION ,  Amit Kumar Srivastava ,  Huimin Chen

Inventor： Amit Kumar Srivastava ,  Huimin Chen

IPC: G06F11/00 ,  G06F11/273 ,  G06F11/22 ,  G06F13/42

Abstract: Techniques and mechanisms for exchanging debug information with a repeater and multiplex logic of a platform. In an embodiment, the multiplex logic can be configured to any of multiple modes including a first mode to exchange debug information between the repeater and debug client logic of the platform. Another of the multiple modes may provide an alternate communication path for exchanging functional data, other than any debug information, between the repeater and a physical layer interface of the platform. In another embodiment, the repeater is compatible with a repeater architecture identified by a universal serial bus standard. The physical layer interface is compatible with an interface specification identified by the same universal bus standard.

公开(公告)号：US20180004699A1

公开(公告)日：2018-01-04

申请号：US15198027

申请日：2016-06-30

Applicant: Duane G. Quiet ,  Amit Kumar Srivastava ,  Kenneth P. Foust

Inventor： Duane G. Quiet ,  Amit Kumar Srivastava ,  Kenneth P. Foust

IPC: G06F13/42 ,  G06F1/32 ,  G06F13/16 ,  G06F13/40

CPC classification number: G06F13/4282 ,  G06F1/3296 ,  G06F13/1673 ,  G06F13/4022

Abstract: In one embodiment, a host controller is to couple to an interconnect to which a plurality of devices may be coupled. The host controller may include: a first driver to drive first information onto the interconnect; and a first receiver to receive second information comprising parameter information of at least one of the plurality of devices from the interconnect. The host controller may further include an integrity control circuit to receive the parameter information of the at least one of the plurality of devices and dynamically update at least one capability of the host controller based at least in part on the parameter information. Other embodiments are described and claimed.

公开(公告)号：US20190227753A1

公开(公告)日：2019-07-25

申请号：US16367608

申请日：2019-03-28

Applicant: Zhenyu Zhu ,  Mikal Hunsaker ,  Karthi R. Vadivelu ,  Rahul Bhatt ,  Kenneth P. Foust ,  Rajesh Bhaskar ,  Amit Kumar Srivastava

Inventor： Zhenyu Zhu ,  Mikal Hunsaker ,  Karthi R. Vadivelu ,  Rahul Bhatt ,  Kenneth P. Foust ,  Rajesh Bhaskar ,  Amit Kumar Srivastava

IPC: G06F3/06 ,  G06F13/38 ,  G06F9/54

Abstract: In one embodiment, a flash sharing controller is to enable a plurality of components of a platform to share a flash memory. The flash sharing controller may include: a flash sharing class layer including a configuration controller to configure the plurality of components to be flash master devices and configure a flash sharing slave device for the flash memory; and a physical layer coupled to the flash sharing class layer to communicate with the plurality of components via a bus. Other embodiments are described and claimed.

公开(公告)号：US20180364774A1

公开(公告)日：2018-12-20

申请号：US15622775

申请日：2017-06-14

Applicant: Chenchu Punnarao Bandi ,  Amit Kumar Srivastava

Inventor： Chenchu Punnarao Bandi ,  Amit Kumar Srivastava

IPC: G06F1/26 ,  H04B3/54 ,  G06F1/06

CPC classification number: G06F1/26 ,  G06F1/06 ,  H04B3/542 ,  H04B3/544

Abstract: A microelectronic assembly may include a first microelectronic device, a second microelectronic device, a first signal link, a second signal link, and a first power connection. The first microelectronic device may include a first interface powered at a first voltage. The second microelectronic device may include a second interface powered at a second voltage. The first signal link may supply a first signal at the first voltage from the first interface to the second interface. The second signal link may supply a second signal at the second voltage from the second interface to the first interface. The first power connection may supply a first reference signal at the first voltage from the first interface to the second interface.