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12 条记录 (耗时 0.024 秒)

    Array-based architecture for molecular electronics
    3.
    发明授权
    Array-based architecture for molecular electronics 有权
    基于阵列的分子电子学架构

    公开(公告)号：US07500213B2

    公开(公告)日：2009-03-03

    申请号：US11344884

    申请日：2006-01-31

    申请人： André DeHon ,  Charles M. Lieber

    发明人： André DeHon ,  Charles M. Lieber

    IPC分类号： G06F17/50

    CPC分类号： G11C13/025 ,  B82Y10/00 ,  G11C8/10 ,  G11C13/0023 ,  G11C13/003 ,  G11C2213/75 ,  G11C2213/77 ,  G11C2213/81 ,  H01L27/28 ,  H01L27/285 ,  H01L51/0508 ,  H01L51/0595

    摘要： An architecture for nanoscale electronics is disclosed. The architecture comprises arrays of crossed nanoscale wires having selectively programmable crosspoints. Nanoscale wires of one array are shared by other arrays, thus providing signal propagation between the arrays. Nanoscale signal restoration elements are also provided, allowing an output of a first array to be used as an input to a second array. Signal restoration occurs without routing of the signal to non-nanoscale wires.

    摘要翻译： 公开了一种用于纳米尺度电子学的架构。 该架构包括具有选择性可编程交叉点的交叉纳米线的阵列。 一个阵列的纳米线由其他阵列共享，从而在阵列之间提供信号传播。 还提供了纳米尺度信号恢复元件，允许将第一阵列的输出用作第二阵列的输入。 信号恢复发生，而不将信号路由到非纳米线。

    Nanoscale wire-based sublithographic programmable logic arrays
    4.
    发明授权
    Nanoscale wire-based sublithographic programmable logic arrays 有权
    纳米线基亚光刻可编程逻辑阵列

    公开(公告)号：US07274208B2

    公开(公告)日：2007-09-25

    申请号：US10856115

    申请日：2004-05-28

    申请人： André DeHon ,  Michael J. Wilson ,  Charles M. Lieber

    发明人： André DeHon ,  Michael J. Wilson ,  Charles M. Lieber

    IPC分类号： G06F7/38 ,  H03K19/173

    CPC分类号： B82Y10/00 ,  G11C11/34 ,  G11C13/02 ,  G11C29/02 ,  G11C29/025 ,  G11C29/08 ,  G11C2213/81 ,  H03K19/17736 ,  H03K19/1778

    摘要： An apparatus and methods for a sublithographic programmable logic array (PLA) are disclosed. The apparatus allows combination of non-restoring, programmable junctions and fixed (non-programmable) restoration logic to implement any logic function or any finite-state machine. The methods disclosed teach how to integrate fixed, restoration logic at sublithographic scales along with programmable junctions. The methods further teach how to integrate addressing from the microscale so that the nanoscale crosspoint junctions can be programmed after fabrication.

    摘要翻译： 公开了一种用于亚光刻可编程逻辑阵列（PLA）的装置和方法。 该装置允许非恢复，可编程结和固定（不可编程）恢复逻辑的组合来实现任何逻辑功能或任何有限状态机。 所公开的方法教导了如何将固定的，恢复逻辑与亚光刻尺以及可编程的结连接在一起。 该方法进一步教导了如何从微尺度集成寻址，使得在制造之后可以对纳米级交叉点结进行编程。

    Intermediate-grain reconfigurable processing device
    6.
    发明授权
    Intermediate-grain reconfigurable processing device 失效
    中粒重配置处理装置

    公开(公告)号：US06266760B1

    公开(公告)日：2001-07-24

    申请号：US09292497

    申请日：1999-04-15

    申请人： André DeHon ,  Ethan Mirsky ,  Thomas F. Knight, Jr.

    发明人： André DeHon ,  Ethan Mirsky ,  Thomas F. Knight, Jr.

    IPC分类号： G06F1516

    CPC分类号： G06F15/8023

    摘要： A programmable integrated circuit utilizes a large number of intermediate-grain processing elements which are multibit processing units arranged in a configurable mesh. The coarse-grain resources, such as memory and processing, are deployable in a way that takes advantage of the opportunities for optimization present in given problems. To accomplish this, the interconnect supports three different modes of operation: a static value in which a value set by the configuration data is provided to a functional unit, static source in which another functional unit serves as the value source, and a dynamic source mode in which the source is determined by the value from another functional unit.

    摘要翻译： 可编程集成电路利用大量的中间粒度处理元件，它们是以可配置的网格布置的多位处理单元。 诸如内存和处理之类的粗粮资源可以利用在给定问题中存在的优化机会的方式进行部署。 为了实现这一点，互连支持三种不同的操作模式：将由配置数据设置的值提供给功能单元的静态值，其他功能单元用作值源的静态源，以及动态源模式 其中源由另一功能单元的值确定。

    Method and apparatus for network with multilayer metalization
    7.
    发明授权
    Method and apparatus for network with multilayer metalization 有权
    多层金属化网络的方法和装置

    公开(公告)号：US07285487B2

    公开(公告)日：2007-10-23

    申请号：US10897582

    申请日：2004-07-23

    申请人： André DeHon ,  Raphael Rubin

    发明人： André DeHon ,  Raphael Rubin

    IPC分类号： H01L21/4763

    CPC分类号： H03K19/17736 ,  G06F15/8023 ,  H03K19/1778 ,  H03K19/17796

    摘要： A network for interconnecting processing element nodes which supports rich interconnection while having a number of switching elements which is linear in the number of processing elements interconnected. Processing elements connect to the lowest level of the tree and the higher levels of the tree make connections between the processing elements. The processing elements may be laid out in a two dimensional grid and one or more horizontal and vertical trees may be used to connect between the processing elements with corner switches used to connect between the horizontal and vertical trees. The levels of the tree can be accommodated in multiple layers of metalization such that the entire layout requires a two-dimensional area which is linear in the number of processing elements supported.

    摘要翻译： 用于互连处理元件节点的网络，其支持丰富的互连，同时具有在互连的处理元件的数量中是线性的多个开关元件。 处理元件连接到树的最低级，树的较高级别使处理元件之间建立连接。 处理元件可以布置在二维网格中，并且一个或多个水平和垂直树可以用于在处理元件之间连接用于在水平和垂直树之间连接的角开关。 树的级别可以容纳在多层金属化中，使得整个布局需要在所支持的处理元件的数量上是线性的二维区域。

    Element placement method and apparatus
    8.
    发明授权
    Element placement method and apparatus 失效
    元件放置方法和装置

    公开(公告)号：US07210112B2

    公开(公告)日：2007-04-24

    申请号：US10643772

    申请日：2003-08-18

    申请人： André DeHon ,  Michael Wrighton

    发明人： André DeHon ,  Michael Wrighton

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5072

    摘要： A method and a device for performing placement of a plurality of elements for circuit design. A potential location is assigned to each element and a placement engine is assigned to each potential location. Pairing operations are performed, in parallel, between placement engines to determine whether to perform exchange of the elements associated with the engines. Exchange determination is based both on a cost function and on randomness considerations. Also self-placement is allowed, where the placement engines are implemented on the same hardware system on which the elements are to be placed.

    摘要翻译： 一种用于执行用于电路设计的多个元件的放置的方法和装置。 潜在的位置被分配给每个元素，并且将布局引擎分配给每个潜在位置。 配对操作并行地执行在放置引擎之间，以确定是否执行与引擎相关联的元件的交换。 交换确定基于成本函数和随机性考虑。 还允许自放置，其中放置引擎在要放置元素的相同硬件系统上实现。

    Fast router and hardware-assisted fast routing method
    10.
    发明授权
    Fast router and hardware-assisted fast routing method 有权
    快速路由器和硬件辅助快速路由方法

    公开(公告)号：US07342414B2

    公开(公告)日：2008-03-11

    申请号：US10356710

    申请日：2003-01-31

    申请人： André DeHon ,  Randy Huang ,  John Wawrzynek

    发明人： André DeHon ,  Randy Huang ,  John Wawrzynek

    IPC分类号： H01L25/00 ,  H03K19/177 ,  G06F7/38

    CPC分类号： H04L49/15 ,  H04L45/26 ,  H04L49/10 ,  H04L49/1507 ,  H04L49/25 ,  H04L49/253 ,  H04L49/30 ,  H04L49/50

    摘要： A fast router and a fast hardware-assisted routing method are disclosed in a network having endpoints, switches and interconnect links. The switches are programmable to allow endpoints to be connected through a particular configuration of switches. The switches also comprise: propagation circuitry which allows a search signal to be propagated through the network; allocation circuitry to set the configuration of switches once a path has been found; and deallocation circuitry to clear a configuration of switches once no path has been found.

    摘要翻译： 在具有端点，交换机和互连链路的网络中公开了快速路由器和快速硬件辅助路由方法。 交换机是可编程的，以允许端点通过特定的交换机配置连接。 开关还包括：允许搜索信号通过网络传播的传播电路; 分配电路，一旦找到路径，就设置开关的配置; 并且一旦没有找到路径，则释放电路以清除开关的配置。