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    METHOD FOR DETERMINING INSTRUCTION ORDER USING TRIGGERS
    1.
    发明申请
    METHOD FOR DETERMINING INSTRUCTION ORDER USING TRIGGERS 审中-公开
    用于确定使用触发器的指令订单的方法

    公开(公告)号：US20140201506A1

    公开(公告)日：2014-07-17

    申请号：US13997021

    申请日：2011-12-30

    申请人： Angshuman Parashar ,  Michael Pellauer ,  Michael Adler ,  Joel Emer

    发明人： Angshuman Parashar ,  Michael Pellauer ,  Michael Adler ,  Joel Emer

    IPC分类号： G06F9/30

    CPC分类号： G06F9/30145 ,  G06F9/30072 ,  G06F9/3013 ,  G06F9/3836

    摘要： A processing engine includes separate hardware components for control processing and data processing. The instruction execution order in such a processing engine may be efficiently determined in a control processing engine based on inputs received by the control processing engine. For each instruction of a data processing engine: a status of the instruction may be set to “ready” based on a trigger for the instruction and the input received in the control processing engine; and execution of the instruction in the data processing engine may be enabled if the status of the instruction is set to “ready” and at least one processing element of the data processing engine is available. The trigger for each instruction may be a function of one or more predicate register of the control processing engine, FIFO status signals or information regarding tags.

    摘要翻译： 处理引擎包括用于控制处理和数据处理的单独的硬件组件。 可以在控制处理引擎中基于由控制处理引擎接收的输入来有效地确定这种处理引擎中的指令执行顺序。 对于数据处理引擎的每个指令：指令的状态可以基于用于指令的触发和在控制处理引擎中接收的输入而被设置为“就绪” 并且如果指令的状态被设置为“就绪”并且数据处理引擎的至少一个处理元件可用，则可以启用数据处理引擎中的指令的执行。 每个指令的触发可以是控制处理引擎的一个或多个谓词寄存器，FIFO状态信号或关于标签的信息的函数。

    Apparatus and method for partitioning a shared cache of a chip multi-processor
    3.
    发明授权
    Apparatus and method for partitioning a shared cache of a chip multi-processor 有权
    用于划分芯片多处理器的共享缓存的装置和方法

    公开(公告)号：US07558920B2

    公开(公告)日：2009-07-07

    申请号：US10882048

    申请日：2004-06-30

    申请人： Matthew Mattina ,  Antonio Juan-Hormigo ,  Joel Emer ,  Ramon Matas-Navarro

    发明人： Matthew Mattina ,  Antonio Juan-Hormigo ,  Joel Emer ,  Ramon Matas-Navarro

    IPC分类号： G06F13/00

    CPC分类号： G06F12/084 ,  G06F12/0864 ,  G06F12/121 ,  G06F2212/6082

    摘要： A method and apparatus for partitioning a shared cache of a chip multi-processor are described. In one embodiment, the method includes a request of a cache block from system memory if a cache miss within a shared cache is detected according to a received request from a processor. Once the cache block is requested, a victim block within the shared cache is selected according to a processor identifier and a request type of the received request. In one embodiment, selection of the victim block according to a processor identifier and request type is based on a partition of a set-associative, shared cache to limit the selection of the victim block from a subset of available cache ways according to the cache partition. Other embodiments are described and claimed.

    摘要翻译： 描述了用于划分芯片多处理器的共享高速缓存的方法和装置。 在一个实施例中，如果根据来自处理器的接收到的请求检测到共享高速缓存内的高速缓存未命中，则该方法包括来自系统存储器的高速缓存块的请求。 一旦请求了高速缓存块，则根据处理器标识符和接收到的请求的请求类型来选择共享高速缓存内的受害块。 在一个实施例中，根据处理器标识符和请求类型来选择受害者块是基于集合关联共享高速缓存的分区，以根据高速缓存分区限制从可用高速缓存路径的子集中选择受害者块 。 描述和要求保护其他实施例。

    Executing checker instructions in redundant multithreading environments
    4.
    发明申请
    Executing checker instructions in redundant multithreading environments 有权
    在冗余多线程环境中执行检查器指令

    公开(公告)号：US20060095821A1

    公开(公告)日：2006-05-04

    申请号：US10953887

    申请日：2004-09-29

    申请人： Shubhendu Mukherjee ,  Joel Emer ,  Steven Reinhardt ,  Christopher Weaver

    发明人： Shubhendu Mukherjee ,  Joel Emer ,  Steven Reinhardt ,  Christopher Weaver

    IPC分类号： G06F9/44

    CPC分类号： G06F11/1494 ,  G06F11/1695

    摘要： A method and apparatus for a checker instruction in a redundant multithreading environment is described. In one embodiment, when RMT requires, a processor may issue a checker instruction in both a leading thread and a trailing thread. The checker instruction may travel down individual pipelines for each thread independently until it reaches a buffer at the end of each pipeline. Then, prior to committing the checker instruction, the checker instruction looks for its counterpart and does a comparison of the instructions. If the checker instructions match, the checker instructions commit and retires otherwise an error is declared.

    摘要翻译： 描述用于冗余多线程环境中的检查指令的方法和装置。 在一个实施例中，当RMT需要时，处理器可以在前导线程和后退线程中发出校验指令。 检查器指令可以独立地沿着每个线程的各个管道下行，直到它到达每个管道末端的缓冲区。 然后，在提交检查指令之前，检验员指令寻找其对应方，并对指令进行比较。 如果检查器指令匹配，则检查器指令提交并退出，否则声明错误。

    Reducing the uncorrectable error rate in a lockstepped dual-modular redundancy system
    6.
    发明申请
    Reducing the uncorrectable error rate in a lockstepped dual-modular redundancy system 失效
    在锁定的双模块冗余系统中减少不可纠正的错误率

    公开(公告)号：US20070022348A1

    公开(公告)日：2007-01-25

    申请号：US11173835

    申请日：2005-06-30

    申请人： Paul Racunas ,  Joel Emer ,  Arijit Biswas ,  Shubhendu Mukherjee ,  Steven Raasch

    发明人： Paul Racunas ,  Joel Emer ,  Arijit Biswas ,  Shubhendu Mukherjee ,  Steven Raasch

    IPC分类号： G06F11/00 ,  G01R31/28

    CPC分类号： G06F11/165 ,  G06F11/1641 ,  G06F11/1658 ,  G06F11/1683

    摘要： Embodiments of apparatuses and methods for reducing the uncorrectable error rate in a lockstepped dual-modular redundancy system are disclosed. In one embodiment, an apparatus includes two processor cores, a micro-checker, a global checker, and fault logic. The micro-checker is to detect whether a value from a structure in one core matches a value from the corresponding structure in the other core. The global checker is to detect lockstep failures between the two cores. The fault logic is to cause the two cores to be resynchronized if there is a lockstep error but the micro-checker has detected a mismatch.

    摘要翻译： 公开了用于降低锁定双模块冗余系统中的不可校正错误率的装置和方法的实施例。 在一个实施例中，装置包括两个处理器核，微检查器，全局检验器和故障逻辑。 微检查器是检测来自一个核心中的结构的值是否与另一个核心中的相应结构的值匹配。 全局检查器是检测两个内核之间的锁步失败。 如果存在锁步错误但微检查器检测到不匹配，则故障逻辑是使两个内核重新同步。

    Buffering unchecked stores for fault detection in redundant multithreading systems using speculative memory support
    7.
    发明申请
    Buffering unchecked stores for fault detection in redundant multithreading systems using speculative memory support 审中-公开
    使用推测内存支持，在冗余多线程系统中缓冲未检查的存储，以进行故障检测

    公开(公告)号：US20050193283A1

    公开(公告)日：2005-09-01

    申请号：US10749618

    申请日：2003-12-30

    申请人： Steven Reinhardt ,  Shubhendu Mukherjee ,  Joel Emer ,  Christopher Weaver

    发明人： Steven Reinhardt ,  Shubhendu Mukherjee ,  Joel Emer ,  Christopher Weaver

    IPC分类号： G06F11/14 ,  G06F11/00

    CPC分类号： G06F11/1497

    摘要： A multithreaded architecture is disclosed for buffering unchecked stores for fault detection in redundant multithreading systems using speculative memory support. In particular, the performance of a SRT processor is enhanced by using speculative memory support to buffer the leading threads stores until they can be compared with their trailing thread counterparts. Buffering these stores in the memory system allows them to be removed from the store buffer. Since the speculative memory system will have greater capacity than the store buffer, additional stores may be buffered before the leading thread will be forced to stall. This will result in an increase in slack between threads, and thus an increase in performance.

    摘要翻译： 公开了一种多线程架构，用于使用推测性内存支持在冗余多线程系统中缓存未检查的存储以进行故障检测。 特别地，SRT处理器的性能通过使用推测性内存支持来缓冲领先的线程存储来增强，直到它们可以与其尾随线程对应来进行比较。 将这些存储缓冲在存储器系统中，可以将它们从存储缓冲区中删除。 由于推测性内存系统的容量会比存储缓冲区大，所以可能会在引导线程被迫停止之前缓存附加存储。 这将导致线程之间的松弛增加，从而导致性能的提高。