公开(公告)号：US20080250073A1

公开(公告)日：2008-10-09

申请号：US11697234

申请日：2007-04-05

申请人： Anil Kumar Nori ,  Laxmi Narsimha Rao Oruganti ,  Subramanian Muralidhar ,  Ambrish Mishra ,  Lev Novik ,  Manikandan Thangarathnam ,  Sankara Subramanian ,  Sudarshan A. Chitre ,  Sitaram C.V. Raju ,  Vijay Tandra Sistla

发明人： Anil Kumar Nori ,  Laxmi Narsimha Rao Oruganti ,  Subramanian Muralidhar ,  Ambrish Mishra ,  Lev Novik ,  Manikandan Thangarathnam ,  Sankara Subramanian ,  Sudarshan A. Chitre ,  Sitaram C.V. Raju ,  Vijay Tandra Sistla

IPC分类号： G06F17/00

CPC分类号： G06F17/30368

摘要： Systems and methods that track changes in a database via a change tracking layer that enables separation of change tracking and change enumeration. Such an arrangement enables multiple change enumeration and sync technologies over a single change tracking layer, while reducing amount of tracking information that are maintained.

摘要翻译： 通过变化跟踪层跟踪数据库中的更改的系统和方法，该变化跟踪层可实现变更跟踪和更改枚举的分离。 这样的布置使得能够通过单个改变跟踪层进行多次更改枚举和同步技术，同时减少维护的跟踪信息的数量。

公开(公告)号：US07818292B2

公开(公告)日：2010-10-19

申请号：US11697234

申请日：2007-04-05

申请人： Anil Kumar Nori ,  Laxmi Narsimha Rao Orugant ,  Subramanian Muralidhar ,  Ambrish Mishra ,  Lev Novik ,  Manikandan Thangarathnam ,  Sankara Subramanian ,  Sudarshan A. Chitre ,  Sitaram C. V. Raju ,  Vijay Tandra Sistla

发明人： Anil Kumar Nori ,  Laxmi Narsimha Rao Orugant ,  Subramanian Muralidhar ,  Ambrish Mishra ,  Lev Novik ,  Manikandan Thangarathnam ,  Sankara Subramanian ,  Sudarshan A. Chitre ,  Sitaram C. V. Raju ,  Vijay Tandra Sistla

IPC分类号： G06F7/00 ,  G06F17/00

CPC分类号： G06F17/30368

摘要： Systems and methods that track changes in a database via a change tracking layer that enables separation of change tracking and change enumeration. Such an arrangement enables multiple change enumeration and sync technologies over a single change tracking layer, while reducing amount of tracking information that are maintained.

摘要翻译： 通过变化跟踪层跟踪数据库中的变化的系统和方法，该变化跟踪层可实现变更跟踪和更改枚举的分离。 这样的布置使得能够通过单个改变跟踪层进行多次更改枚举和同步技术，同时减少维护的跟踪信息的数量。

公开(公告)号：US08981951B2

公开(公告)日：2015-03-17

申请号：US13504482

申请日：2009-11-05

申请人： Sankara Subramanian ,  Simon Richards ,  Alan Wixon

发明人： Sankara Subramanian ,  Simon Richards ,  Alan Wixon

IPC分类号： G08B21/00 ,  H02H7/30 ,  H02H3/00

CPC分类号： H02H7/30 ,  H02H3/006

摘要： A method of monitoring the grading margin between at least two time-current characteristics of Intelligent Electronic Devices (IEDA, IEDB) installed in an electrical power system, each Intelligent Electronic Device comprising a counting means, the grading margin comprising a safety margin set by a user, characterized in that it comprises, when a fault occurs which causes a fault current in the electrical power system, a step of providing a warning to the user when the safety margin is infringed upon.

摘要翻译： 一种监视安装在电力系统中的智能电子设备（IEDA，IEDB）的至少两个时间电流特性之间的分级余量的方法，每个智能电子设备包括计数装置，所述分级余量包括由 用户，其特征在于，当发生导致电力系统中的故障电流的故障时，包括当安全边际被侵害时向用户提供警告的步骤。

公开(公告)号：US20060170094A1

公开(公告)日：2006-08-03

申请号：US11050330

申请日：2005-02-02

申请人： Sankara Subramanian ,  Abhay Watwe

发明人： Sankara Subramanian ,  Abhay Watwe

IPC分类号： H01L23/34

CPC分类号： H01L23/3675 ,  H01L21/563 ,  H01L23/3733 ,  H01L23/42 ,  H01L25/0655 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2924/15311 ,  H01L2924/16152

摘要： An integral heat spreader is disclosed wherein its physical characteristics are modified in regions between adjacent semiconductor devices. The modification improves the reliability of the semiconductor devices by reducing stiffness of the integral heat spreader.

摘要翻译： 公开了一种整体散热器，其中其物理特性在相邻半导体器件之间的区域中被修改。 该修改通过降低整体散热器的刚度来提高半导体器件的可靠性。

公开(公告)号：US20070004085A1

公开(公告)日：2007-01-04

申请号：US11169518

申请日：2005-06-29

申请人： Patricia Brusso ,  Mitul Modi ,  Carolyn McCormick ,  Ruben Cadena ,  Sankara Subramanian ,  Edward Martin

发明人： Patricia Brusso ,  Mitul Modi ,  Carolyn McCormick ,  Ruben Cadena ,  Sankara Subramanian ,  Edward Martin

IPC分类号： H01L21/00

CPC分类号： H05K1/115 ,  G06F1/16 ,  H01L24/81 ,  H01L24/90 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2224/90 ,  H01L2924/14 ,  H01L2924/3511 ,  H05K3/305 ,  H05K3/3436 ,  H05K2201/10378 ,  H05K2203/1105 ,  Y02P70/613 ,  H01L2924/00

摘要： An underfill device and method have been are provided. Advantages of devices and methods shown include dissipation of stresses at an interface between components such as a chip package and an adjacent circuit board. Another advantage includes faster manufacturing time and ease of manufacture using underfill devices and methods shown. An underfill assembly can be pre made with conductive structures included within the underfill assembly. Steps such as flowing epoxy and curing can be eliminated or performed concurrently with other manufacturing steps.

摘要翻译： 提供了底部填充装置和方法。 显示的装置和方法的优点包括在诸如芯片封装和相邻电路板的部件之间的界面处的应力耗散。 另一个优势包括加快制造时间和使用底部填充装置的制造方便以及所示的方法。 底部填充组件可以预先制成包含在底部填充组件内的导电结构。 步骤如流动的环氧树脂和固化可以消除或与其他制造步骤同时进行。

公开(公告)号：US20080054446A1

公开(公告)日：2008-03-06

申请号：US11977980

申请日：2007-10-26

申请人： Mitul Modi ,  Patricia Brusso ,  Ruben Cadena ,  Carolyn McCormick ,  Sankara Subramanian

发明人： Mitul Modi ,  Patricia Brusso ,  Ruben Cadena ,  Carolyn McCormick ,  Sankara Subramanian

IPC分类号： H01L23/12 ,  H05K7/00

CPC分类号： H01L23/145 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/15311 ,  H05K1/0271 ,  H05K3/4602 ,  H05K2201/0133 ,  H05K2201/068 ,  H01L2924/00 ,  H01L2224/0401

摘要： An IC package is disclosed that comprises a core region disposed between upper and lower build-up layer regions. In one embodiment, the core region comprises a low modulus material. In an alternative embodiment the core region comprises a medium modulus material. In an alternative embodiment, the core material is selected based upon considerations such as it modulus, its coefficient of thermal expansion, and/or the resulting total accumulated strain. In an alternative embodiment, boundaries with respect to the softness of the core material are established be considering the reflective density in opposing conductive build-up layers above and below the core region.

摘要翻译： 公开了一种IC封装，其包括设置在上部和下部积聚层区域之间的芯区域。 在一个实施例中，芯区域包括低模量材料。 在替代实施例中，芯区域包括中等模量材料。 在替代实施例中，基于诸如其模量，其热膨胀系数和/或所得到的总累积应变的考虑来选择芯材料。 在替代实施例中，考虑到核心区域上方和下方的相对的导电堆积层中的反射密度，建立了关于芯材料的柔软度的边界。

公开(公告)号：US20070026575A1

公开(公告)日：2007-02-01

申请号：US11167073

申请日：2005-06-24

申请人： Sankara Subramanian ,  Mitul Modi ,  Ibrahim Bekar

发明人： Sankara Subramanian ,  Mitul Modi ,  Ibrahim Bekar

IPC分类号： H01L21/00

CPC分类号： H01L21/563 ,  H01L24/29 ,  H01L24/81 ,  H01L24/83 ,  H01L2224/16225 ,  H01L2224/2919 ,  H01L2224/73203 ,  H01L2224/81193 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2224/83101 ,  H01L2224/83192 ,  H01L2224/83851 ,  H01L2224/83856 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2924/00014 ,  H01L2924/0665

摘要： A more reliable and easier to manufacture underfill assembly is shown. Underfill layers are shown that are manufacturable separately from an assembly operation. In one example, underfill layers have the ability for pick and place operations during assembly. Another advantage of underfill layers provided includes self aligning holes that aid in placing semiconductor chips over an appropriate location on a substrate. Another advantage of selected underfill layers includes pre-formed conductive plugs within an underfill layer that eliminate the need for forming solder bumps on an adjacent component surface.

摘要翻译： 显示出更可靠和更容易制造的底部填充组件。 示出了与组装操作分开制造的底部填充层。 在一个示例中，底部填充层具有在组装期间拾取和放置操作的能力。 提供的底部填充层的另一个优点包括有助于将半导体芯片放置在衬底上的合适位置上的自对准孔。 选择的底部填充层的另一个优点包括在底部填充层内的预先形成的导电插塞，其消除了在相邻部件表面上形成焊料凸块的需要。

公开(公告)号：US20120212348A1

公开(公告)日：2012-08-23

申请号：US13504482

申请日：2009-11-05

申请人： Sankara Subramanian ,  Simon Richards ,  Alan Wixon

发明人： Sankara Subramanian ,  Simon Richards ,  Alan Wixon

IPC分类号： G08B21/00

CPC分类号： H02H7/30 ,  H02H3/006

摘要： A method of monitoring the grading margin between at least two time-current characteristics of Intelligent Electronic Devices (IEDA, IEDB) installed in an electrical power system, each Intelligent Electronic Device comprising a counting means, the grading margin comprising a safety margin set by a user, characterized in that it comprises, when a fault occurs which causes a fault current in the electrical power system, a step of providing a warning to the user when the safety margin is infringed upon.

摘要翻译： 一种监测安装在电力系统中的智能电子设备（IEDA，IEDB）的至少两个时间电流特性之间的分级余量的方法，每个智能电子设备包括计数装置，所述分级余量包括由 用户，其特征在于，当发生导致电力系统中的故障电流的故障时，包括在安全边际被侵害时向用户提供警告的步骤。

公开(公告)号：US20080057630A1

公开(公告)日：2008-03-06

申请号：US11978059

申请日：2007-10-26

申请人： Mitul Modi ,  Patricia Brusso ,  Ruben Cadena ,  Carolyn McCormick ,  Sankara Subramanian

发明人： Mitul Modi ,  Patricia Brusso ,  Ruben Cadena ,  Carolyn McCormick ,  Sankara Subramanian

IPC分类号： H01L21/00

CPC分类号： H01L23/145 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/15311 ,  H05K1/0271 ,  H05K3/4602 ,  H05K2201/0133 ,  H05K2201/068 ,  H01L2924/00 ,  H01L2224/0401

摘要： An IC package is disclosed that comprises a core region disposed between upper and lower build-up layer regions. In one embodiment, the core region comprises a low modulus material. In an alternative embodiment the core region comprises a medium modulus material. In an alternative embodiment, the core material is selected based upon consideration such as its modulus, its coefficient of thermal expansion, and/or resulting total accumulated strain. In an alternative embodiment, boundaries with respect to the softness of the core material are established by considering the relative density in opposing conductive build-up layers above and below the core region.

摘要翻译： 公开了一种IC封装，其包括设置在上部和下部积聚层区域之间的芯区域。 在一个实施例中，芯区域包括低模量材料。 在替代实施例中，芯区域包括中等模量材料。 在替代实施例中，基于诸如其模量，其热膨胀系数和/或所得到的总累积应变的考虑来选择芯材料。 在替代实施例中，通过考虑在芯区域上方和下方的相对的导电堆积层中的相对密度来建立关于芯材料的柔软度的边界。

公开(公告)号：US20060261464A1

公开(公告)日：2006-11-23

申请号：US11134784

申请日：2005-05-20

申请人： Mitul Modi ,  Patricia Brusso ,  Ruben Cadena ,  Carolyn McCormick ,  Sankara Subramanian

发明人： Mitul Modi ,  Patricia Brusso ,  Ruben Cadena ,  Carolyn McCormick ,  Sankara Subramanian

IPC分类号： H01L23/12 ,  H05K7/00

CPC分类号： H01L23/145 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/15311 ,  H05K1/0271 ,  H05K3/4602 ,  H05K2201/0133 ,  H05K2201/068 ,  H01L2924/00 ,  H01L2224/0401

摘要： An IC package is disclosed that comprises a core region disposed between upper and lower build-up layer regions. In one embodiment, the core region comprises a low modulus material. In an alternative embodiment the core region comprises a medium modulus material. In an alternative embodiment, the core material is selected based upon considerations such as its modulus, its coefficient of thermal expansion, and/or the resulting total accumulated strain. In an alternative embodiment, boundaries with respect to the softness of the core material are established by considering the relative density in opposing conductive build-up layers above and below the core region.

摘要翻译： 公开了一种IC封装，其包括设置在上部和下部积聚层区域之间的芯区域。 在一个实施例中，芯区域包括低模量材料。 在替代实施例中，芯区域包括中等模量材料。 在替代实施例中，基于诸如其模量，其热膨胀系数和/或所得到的总累积应变的考虑来选择芯材料。 在替代实施例中，通过考虑在芯区域上方和下方的相对的导电堆积层中的相对密度来建立关于芯材料的柔软度的边界。