公开(公告)号：US07737051B2

公开(公告)日：2010-06-15

申请号：US10797876

申请日：2004-03-10

申请人： Anthony Dip ,  Pradip K. Roy ,  Sanjeev Kaushal ,  Allen J. Leith ,  Seungho Oh ,  Raymond Joe

发明人： Anthony Dip ,  Pradip K. Roy ,  Sanjeev Kaushal ,  Allen J. Leith ,  Seungho Oh ,  Raymond Joe

IPC分类号： H01L21/36

CPC分类号： H01L21/31604 ,  H01L21/02142 ,  H01L21/0217 ,  H01L21/02175 ,  H01L21/02318 ,  H01L21/02323 ,  H01L21/02337 ,  H01L21/02362 ,  H01L21/31637 ,  H01L21/31641 ,  H01L21/31645 ,  H01L21/3185 ,  Y10T29/41

摘要： A method for using a silicon germanium (SiGe) surface layer to integrate a high-k dielectric layer into a semiconductor device. The method forms a SiGe surface layer on a substrate and deposits a high-k dielectric layer on the SiGe surface layer. An oxide layer, located between the high-k dielectric layer and an unreacted portion of the SiGe surface layer, is formed during one or both of deposition of the high-k dielectric layer and an annealing process after deposition of the high-k dielectric layer. The method further includes forming an electrode layer on the high-k dielectric layer.

摘要翻译： 一种使用硅锗（SiGe）表面层将高k电介质层集成到半导体器件中的方法。 该方法在衬底上形成SiGe表面层，并在SiGe表面层上沉积高k电介质层。 在高k电介质层的沉积和沉积高k电介质层之间的退火工艺中的一个或两个期间，形成位于高k电介质层和SiGe表面层的未反应部分之间的氧化物层 。 该方法还包括在高k电介质层上形成电极层。

公开(公告)号：US08932116B2

公开(公告)日：2015-01-13

申请号：US13612135

申请日：2012-09-12

申请人： Manish Deopura ,  Hem M. Vaidya ,  Pradip K. Roy

发明人： Manish Deopura ,  Hem M. Vaidya ,  Pradip K. Roy

IPC分类号： B24B37/26 ,  B24D15/04 ,  B24D18/00 ,  B29C33/42 ,  B29C33/56 ,  B29C33/38 ,  B29C33/40 ,  B29K83/00

CPC分类号： B24B37/26 ,  B24D15/04 ,  B24D18/0009 ,  B29C33/3842 ,  B29C33/405 ,  B29C33/424 ,  B29C33/565 ,  B29K2083/00 ,  B33Y80/00

摘要： Methods for producing in-situ grooves in CMP pads are provided. In general, the methods for producing in-situ grooves comprise the steps of patterning a silicone lining, placing the silicone lining in, or on, a mold, adding CMP pad material to the silicone lining, and allowing the CMP pad to solidify. CMP pads comprising novel groove designs are also described. For example, described here are CMP pads comprising concentric circular grooves and axially curved grooves, reverse logarithmic grooves, overlapping circular grooves, lassajous groves, double spiral grooves, and multiply overlapping axially curved grooves. The CMP pads may be made from polyurethane, and the grooves produced therein may be made by a method from the group consisting of silicone lining, laser writing, water jet cutting, 3-D printing, thermoforming, vacuum forming, micro-contact printing, hot stamping, and mixtures thereof.

摘要翻译： 提供了用于在CMP垫中产生原位凹槽的方法。 通常，用于制造原位槽的方法包括将硅衬里图案化，将硅衬里放置在模具中或模具上，将CMP衬垫材料添加到硅衬里，并允许CMP垫固化的步骤。 还描述了包括新颖凹槽设计的CMP垫。 例如，这里描述的是包括同心圆形槽和轴向弯曲槽，反向对数槽，重叠圆形槽，拉索格，双螺旋槽和多重重叠的轴向曲线槽的CMP垫。 CMP垫可以由聚氨酯制成，并且其中产生的凹槽可以由以下方法制成：由硅胶衬里，激光书写，水射流切割，3-D印刷，热成型，真空成型，微接触印刷， 热冲压及其混合物。

公开(公告)号：US08029849B2

公开(公告)日：2011-10-04

申请号：US10944209

申请日：2004-09-17

申请人： Stephen B. Richey ,  Guoshen Yang ,  Myung Hee Lohman ,  Mary E. Steele ,  Brian M. Reifsteck ,  Pradip K. Roy ,  Sylvia L. Schonauer

发明人： Stephen B. Richey ,  Guoshen Yang ,  Myung Hee Lohman ,  Mary E. Steele ,  Brian M. Reifsteck ,  Pradip K. Roy ,  Sylvia L. Schonauer

IPC分类号： A23G3/54

CPC分类号： A23G3/2015 ,  A23G3/0021 ,  A23G3/0242 ,  A23G3/2023 ,  A23G3/42 ,  A23G3/48 ,  A23G3/54 ,  A23G4/20

摘要： A multi-piece food product (10) comprising a plurality of strands (12A-12K) that are extruded and aggregated to form an aesthetically pleasing food product is provided. A formulation used to make each of the strands (12A-12K) includes a mixture comprising at least 20% sweetener, at least 15% starchy material, and at least 1% fruit by weight based a total dry weight of the mixture to yield a starch-based confectionary food product. One process for forming the multi-piece food product (10) includes extruding a food stream from a slurry, dividing the food stream into three separate food streams (24A, 24B), injecting color, flavor, and ascorbic acid into the food streams (24A, 24B), conveying the food streams (24A, 24B) into a former (26) and extruding the strands (12A-12K) therefrom, forming the strands (12A, 12B) into an aggregate food mass (31), cooling the food mass (31), and cutting the food mass (31) into individual portions.

摘要翻译： 提供了一种多片食品（10），其包括被挤出和聚集以形成美学上令人满意的食品的多根股线（12A-12K）。 用于制备每条链（12A-12K）的制剂包含基于混合物的总干重的包含至少20％甜味剂，至少15％淀粉质材料和至少1重量％果糖的混合物，以产生 淀粉型糖果食品。 用于形成多片食品（10）的一个方法包括从浆料挤出食物流，将食物流分成三个独立的食物流（24A，24B），将颜色，风味剂和抗坏血酸注入食物流中 24A，24B），将食物流（24A，24B）输送到成形器（26）中并从其中挤出股线（12A-12K），将股线（12A，12B）形成为集料食品（31），冷却 食物块（31），并将食物块（31）切割成单独的部分。

公开(公告)号：US20090053976A1

公开(公告)日：2009-02-26

申请号：US11884829

申请日：2006-02-21

申请人： Pradip K. Roy ,  Manish Deopura ,  Sudhanshu Misra

发明人： Pradip K. Roy ,  Manish Deopura ,  Sudhanshu Misra

IPC分类号： B24D18/00 ,  B24D3/00 ,  B24D11/00 ,  B24B7/22

CPC分类号： B24B37/24 ,  B33Y80/00

摘要： The present application relates to polishing pads for chemical mechanical planarization (CMP) of substrates, and methods of fabrication and use thereof. The pads described in this invention are customized to polishing specifications where specifications include (but not limited to) to the material being polished, chip design and architecture, chip density and pattern density, equipment platform and type of slurry used. These pads can be designed with a specialized polymeric nano-structure with a long or short range order which allows for molecular level tuning achieving superior thermo-mechanical characteristics. More particularly, the pads can be designed and fabricated so that there is both uniform and nonuniform spatial distribution of chemical and physical properties within the pads. In addition, these pads can be designed to tune the coefficient of friction by surface engineering, through the addition of solid lubricants, and creating low shear integral pads having multiple layers of polymeric material which form an interface parallel to the polishing surface. The pads can also have controlled porosity, embedded abrasive, novel grooves on the polishing surface, for slurry transport, which are produced in situ, and a transparent region for endpoint detection.

摘要翻译： 本申请涉及用于基板的化学机械平面化（CMP）的抛光垫及其制造和使用方法。 本发明中描述的焊盘定制为抛光规格，其中规格包括（但不限于）被抛光材料，芯片设计和结构，芯片密度和图案密度，设备平台和使用的浆料类型。 这些垫可以设计成具有长或短范围顺序的专门的聚合物纳米结构，其允许分子水平调节实现优异的热机械特性。 更具体地，可以设计和制造焊盘，使得焊盘内的化学和物理性质均匀和不均匀的空间分布。 此外，这些垫可以被设计成通过表面工程，通过添加固体润滑剂来调节摩擦系数，并且产生具有形成与抛光表面平行的界面的多层聚合材料的低剪切整体垫。 焊盘还可以具有受控的孔隙率，嵌入式研磨剂，抛光表面上的新型凹槽，用于原位生产的浆料输送，以及用于端点检测的透明区域。

公开(公告)号：US06544107B2

公开(公告)日：2003-04-08

申请号：US09785756

申请日：2001-02-16

申请人： Sudhanshu Misra ,  Pradip K. Roy

发明人： Sudhanshu Misra ,  Pradip K. Roy

IPC分类号： B24B100

CPC分类号： B24B37/26 ,  B24B37/24 ,  B24D7/14

摘要： The present invention provides a composite polishing pad, comprising. In an advantageous embodiment, the composite polishing pad includes a polishing pad member comprising a material having a predetermined hardness and an annular support member underlying a periphery of the polishing pad member, the annular support member having a hardness less than the predetermined hardness of the polishing pad member.

公开(公告)号：US06313021B1

公开(公告)日：2001-11-06

申请号：US09416491

申请日：1999-10-12

申请人： Sailesh M. Merchant ,  Joseph R. Radosevich ,  Pradip K. Roy

发明人： Sailesh M. Merchant ,  Joseph R. Radosevich ,  Pradip K. Roy

IPC分类号： H01L213205

CPC分类号： H01L21/28035 ,  H01L21/28044 ,  H01L21/28061 ,  H01L21/823835 ,  H01L21/823842 ,  H01L29/4933 ,  H01L29/4941

摘要： The present invention provides a process for forming a sub-micron p-type metal oxide semiconductor (PMOS) structure on a semiconductor substrate. The process includes forming a gate oxide on the semiconductor substrate, forming a gate layer on the gate oxide by depositing a first gate layer on the gate oxide at a first deposition rate and depositing a second gate layer on the first layer at a second deposition rate to provide an improved stress accommodation within the gate structure. The process further includes forming a silicide dopant barrier on the gate. Due to the presence of the improved stress accommodation in the gate, the integrity of the silicide dopant barrier is substantially enhanced. This increased silicide integrity prevents significant damage to the silicide dopant barrier layer during subsequent fabrication processes. As such, the dopant barrier is able to provide the intended degree of resistance to dopant penetration, for example boron, during the formation of source and drain regions adjacent the gate structure.

摘要翻译： 本发明提供了一种在半导体衬底上形成亚微米p型金属氧化物半导体（PMOS）结构的方法。 该工艺包括在半导体衬底上形成栅极氧化物，通过以第一沉积速率沉积栅极氧化物上的第一栅极层，以栅极氧化物形成栅极层，并以第二沉积速率在第一层上沉积第二栅极层 以在门结构内提供改进的应力调节。 该工艺还包括在栅极上形成硅化物掺杂剂阻挡层。 由于在栅极中存在改善的应力调节，硅化物掺杂剂势垒的完整性显着增强。 这种增加的硅化物完整性防止在随后的制造工艺期间对硅化物掺杂剂阻挡层的显着损坏。 因此，在形成与栅极结构相邻的源极和漏极区域期间，掺杂物势垒能够提供对掺杂剂穿透（例如硼）的预期程度的阻抗。

公开(公告)号：US06255128B1

公开(公告)日：2001-07-03

申请号：US09130240

申请日：1998-08-06

申请人： Carlos M. Chacon ,  Pradip K. Roy

发明人： Carlos M. Chacon ,  Pradip K. Roy

IPC分类号： B01R3126

CPC分类号： G01N27/002 ,  H01L22/12

摘要： The present invention provides a non-contact method for determining whether a contaminant is present in a semiconductor wafer having a substrate/dielectric interface formed thereon. in one advantageous embodiment, the method comprises field inducing a junction in equilibrium inversion in the semiconductor wafer device. A conventional corona source may be used to induce the junction to equilibrium inversion. This particular embodiment further includes forming a contaminant junction near the substrate/dielectric interface when the contaminant is present in the semiconductor wafer by adding charge and pulsing the junction out of equilibrium. A surface voltage measurement, which may be taken with a Kelvin probe, is obtained by measuring a change in a surface voltage as a function of time. The method further includes determining whether the contaminant is present in the semiconductor wafer from the change in the surface voltage. When the contaminant is present in the device, the change in the surface voltage is negligible. This negligible change is in stark contrast to the change in surface voltage that occurs in a non-contaminated device. The data obtained from these surface voltages can be plotted with conventional devices to yield the change in surface voltage with respect to time.

摘要翻译： 本发明提供了一种用于确定在其上形成有衬底/电介质界面的半导体晶片中是否存在污染物的非接触方法。 在一个有利的实施例中，该方法包括在半导体晶片装置中的场平衡反转中的场感应。 传统的电晕源可以用来诱导结到平衡反转。 该特定实施例还包括当通过添加电荷并将结合脉冲到平衡之外，当污染物存在于半导体晶片中时，在衬底/电介质界面附近形成污染物结。 通过测量作为时间的函数的表面电压的变化可获得可以用开尔文探针进行的表面电压测量。 该方法还包括根据表面电压的变化确定污染物是否存在于半导体晶片中。 当设备中存在污染物时，表面电压的变化可以忽略不计。 这个微不足道的变化与在非污染设备中发生的表面电压的变化形成鲜明的对比。 从这些表面电压获得的数据可以用常规装置绘制，以产生相对于时间的表面电压的变化。

公开(公告)号：US06246095B1

公开(公告)日：2001-06-12

申请号：US09146418

申请日：1998-09-03

申请人： David C. Brady ,  Yi Ma ,  Pradip K. Roy

发明人： David C. Brady ,  Yi Ma ,  Pradip K. Roy

IPC分类号： H01L2976

CPC分类号： H01L21/28185 ,  H01L21/28202 ,  H01L21/28211 ,  H01L29/513 ,  H01L29/518

摘要： This invention includes a novel synthesis of a three-step process of growing, depositing and growing Si02 under low pressure, e.g., 0.2-10 Torr, to generate high quality, robust and reliable gate oxides for sub 0.5 micron technologies. The first layer, 1.0-3.0 nm is thermally grown for passivation of the Si-semiconductor surface. The second deposited layer 1.0-5.0 nm forms an interface with the first grown layer. During the third step of the synthesis densification of the deposited oxide layers occurs with a simultaneous removal of the interface traps at the interface and growth of a stress-modulated Si02 occurs at the Si/first grown layer interface in the presence of a stress-accommodating interface layer resulting in a planar and stress-reduced Si/SiO2 interface. The entire synthesis is done under low-pressure (e.g., 0.2-10 Torr) for slowing down the oxidation kinetics to achieve ultrathin sublayers and may be done in a single low-pressure furnace by clustering all three steps. For light nitrogen-incorporation (

摘要翻译： 本发明包括在低压例如0.2-10托下生长，沉积和生长SiO 2的三步法的新型合成，以产生用于亚0.5微米技术的高质量，坚固和可靠的栅极氧化物。 对第一层，1.0-3.0nm进行热生长以钝化Si半导体表面。 第二沉积层1.0-5.0nm与第一生长层形成界面。 在沉积的氧化物层的合成致密化的第三步骤中，同时去除界面处的界面陷阱并且在应力容纳的存在下在Si /第一生长层界面处发生应力调制的SiO 2的生长 界面层，产生平面和应力降低的Si / SiO 2界面。 整个合成在低压（例如，0.2-10托）下进行，以减缓氧化动力学以达到超薄亚层，并且可以通过聚集所有三个步骤在单个低压炉中进行。 对于某些器件的轻氮掺入（<5％），通常由于提高的耐硼性和其他掺杂剂扩散性和热载流子特性而需要，因此在层叠氧化物合成的每个步骤期间都使用氧化剂中的N2O或NO。 平面和应力降低的Si / SiO 2界面特性是层叠氧化物的独特标志，其改善了栅极氧化物对ULSI处理的鲁棒性，导致器件参数（例如，阈值电压跨导），迁移率降低和对热载流子的耐受性降低 和福勒 - 诺德海姆的压力。

公开(公告)号：US5523259A

公开(公告)日：1996-06-04

申请号：US349649

申请日：1994-12-05

申请人： Sailesh M. Merchant ,  Arun K. Nanda ,  Pradip K. Roy

发明人： Sailesh M. Merchant ,  Arun K. Nanda ,  Pradip K. Roy

IPC分类号： H01L21/28 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/52 ,  H01L23/522 ,  H01L23/532

CPC分类号： H01L23/5329 ,  H01L23/5226 ,  H01L2924/0002

摘要： In an integrated circuit, an opening (e.g., via or window) is filled with an Al-based plug which has essentially a orientation and comprises at most three grains. These characteristics are achieved by first depositing a texture control Ti layer having substantially a (002) basal plane orientation followed by at least three Al-based sublayers. The grain sizes and deposition conditions are controlled in such a way that during deposition of the third sublayer, the microstructure of the plug adjusts itself to produce a single grain (or at most three).

摘要翻译： 在集成电路中，开口（例如，通孔或窗口）填充有基本上为111°取向且至多包含三个晶粒的Al-基塞。 这些特性通过首先沉积具有基本上（002）基面平面取向的纹理控制Ti层，然后是至少三个基于Al的子层来实现。 晶粒尺寸和沉积条件被控制为在沉积第三子层期间，插塞的微观结构自身调整以产生单个颗粒（或至多三个）。

公开(公告)号：US5298436A

公开(公告)日：1994-03-29

申请号：US76949

申请日：1993-06-16

申请人： Joseph R. Radosevich ,  Pradip K. Roy

发明人： Joseph R. Radosevich ,  Pradip K. Roy

IPC分类号： H01L21/8247 ,  H01L21/28 ,  H01L21/3205 ,  H01L29/788 ,  H01L29/792 ,  H01L21/20

CPC分类号： H01L21/32055 ,  H01L21/28158 ,  H01L21/28273

摘要： A high quality dielectric layer, typically silicon dioxide, is formed on a multi-layer deposited semiconductor structure, typically polysilicon or amorphous silicon. The multi-layer structure is formed by varying the silicon deposition rate so as to obtain a low stress deposited silicon structure. The low stress allows for a higher quality dielectric to be formed on the exposed top surface. One application is for thin film transistor gate oxides. Other applications included capacitor dielectrics and the tunnel oxide on the floating gate of EEPROMs.

摘要翻译： 通常在多层沉积的半导体结构（通常为多晶硅或非晶硅）上形成高质量的介电层，通常为二氧化硅。 通过改变硅沉积速率形成多层结构，以获得低应力淀积硅结构。 低应力允许在暴露的顶表面上形成更高质量的电介质。 一种应用是薄膜晶体管栅极氧化物。 其他应用包括电容器电介质和隧道氧化物在EEPROM的浮动栅极上。