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    SELECTIVE LOW TEMPERATURE EPITAXIAL DEPOSITION PROCESS
    1.
    发明申请
    SELECTIVE LOW TEMPERATURE EPITAXIAL DEPOSITION PROCESS 有权

    公开(公告)号：US20220238650A1

    公开(公告)日：2022-07-28

    申请号：US17231087

    申请日：2021-04-15

    Applicant: Applied Materials, Inc.

    Inventor： Chen-Ying WU ,  Abhishek DUBE ,  Yi-Chiau HUANG

    IPC: H01L29/08 ,  H01L29/66 ,  H01L29/167 ,  H01L21/02 ,  H01L21/225

    Abstract: A method for the selective formation of epitaxial layers is described herein. In the method, epitaxial layers are deposited to form source and drain regions around a horizontal gate all around (hGAA structure). The method includes co-flowing a combination of chlorinated silicon containing precursors, antimony containing precursors, and n-type dopant precursors. The resulting source and drain regions are selectively grown from crystalline nanosheets or nanowires of the hGAA structure over the non-crystalline gate structure and dielectric layers. The source and drain regions are predominantly grown in a direction.

    METHODS AND APPARATUS FOR ANISOTROPIC FILM GROWTH, AND RELATED DEVICES
    3.
    发明申请
    METHODS AND APPARATUS FOR ANISOTROPIC FILM GROWTH, AND RELATED DEVICES 有权

    公开(公告)号：US20250132154A1

    公开(公告)日：2025-04-24

    申请号：US18491584

    申请日：2023-10-20

    Applicant: Applied Materials, Inc.

    Inventor： Chen-Ying WU ,  Abhishek DUBE ,  Zuoming ZHU

    IPC: H01L21/02 ,  C30B25/16 ,  C30B29/52 ,  H01L27/088

    Abstract: The present disclosure relates to semiconductor processing methods for anisotropic film growth. The method includes heating a substrate positioned in a processing chamber. The method includes flowing one or more process gases over the substrate. The one or more process gases include trichlorosilane (TCS) and hydrochloric acid. The method includes depositing one or more layers on one or more fins on the substrate. The deposition of the one or more layers includes forming the one or more layers at a first growth rate along a first dimension and a second growth rate along a second dimension, and the second growth rate is faster than the first growth rate.

    ANISOTROPIC SIGE:B EPITAXIAL FILM GROWTH FOR GATE ALL AROUND TRANSISTOR
    8.
    发明申请
    ANISOTROPIC SIGE:B EPITAXIAL FILM GROWTH FOR GATE ALL AROUND TRANSISTOR 有权

    公开(公告)号：US20230037320A1

    公开(公告)日：2023-02-09

    申请号：US17396371

    申请日：2021-08-06

    Applicant: Applied Materials, Inc.

    Inventor： Chen-Ying WU ,  Zhiyuan YE ,  Xuebin LI ,  Sathya CHARY ,  Yi-Chiau HUANG ,  Saurabh CHOPRA

    IPC: H01L21/02 ,  H01L29/423 ,  H01L29/08 ,  H01L29/66

    Abstract: Embodiments described herein relate to a method of epitaxial deposition of p-channel metal oxide semiconductor (MMOS) source/drain regions within horizontal gate all around (hGAA) device structures. Combinations of precursors are described herein, which grow of the source/drain regions on predominantly surfaces with reduced or negligible growth on surfaces. Therefore, growth of the source/drain regions is predominantly located on the top surface of a substrate instead of the alternating layers of the hGAA structure. The precursor combinations include a silicon containing precursor, a germanium containing precursor, and a boron containing precursor. At least one of the precursors further includes chlorine.

    SELECTIVE METHODS FOR FABRICATING DEVICES AND STRUCTURES
    9.
    发明申请
    SELECTIVE METHODS FOR FABRICATING DEVICES AND STRUCTURES 有权

    公开(公告)号：US20220310390A1

    公开(公告)日：2022-09-29

    申请号：US17616131

    申请日：2020-06-10

    Applicant: Applied Materials, Inc.

    Inventor： Yi-Chiau HUANG ,  Chen-Ying WU ,  Abhishek DUBE ,  Chia Cheng CHIN ,  Saurabh CHOPRA

    IPC: H01L21/02 ,  H01L29/08 ,  H01L21/8234 ,  C30B25/18 ,  C30B29/52 ,  C23C16/06

    Abstract: One or more embodiments described herein relate to selective methods for fabricating devices and structures. In these embodiments, the devices are exposed inside the process volume of a process chamber. Precursor gases are flowed in the process volume at certain flow ratios and at certain process conditions. The process conditions described herein result in selective epitaxial layer growth on the {100} planes of the crystal planes of the devices, which corresponds to the top of each of the fins. Additionally, the process conditions result in selective etching of the {110} plane of the crystal planes, which corresponds to the sidewalls of each of the fins. As such, the methods described herein provide a way to grow or etch epitaxial films at different crystal planes. Furthermore, the methods described herein allow for simultaneous epitaxial film growth and etch to occur on the different crystal planes.

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