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    Image compressing coding apparatus and method for detecting a top position of an image in a buffer overflow
    1.
    发明授权
    Image compressing coding apparatus and method for detecting a top position of an image in a buffer overflow 失效
    用于检测缓冲器溢出中的图像的顶部位置的图像压缩编码装置和方法

    公开(公告)号：US06907068B2

    公开(公告)日：2005-06-14

    申请号：US09922695

    申请日：2001-08-07

    申请人： Hiroshi Segawa ,  Satoshi Kumaki ,  Yoshinori Matsuura

    发明人： Hiroshi Segawa ,  Satoshi Kumaki ,  Yoshinori Matsuura

    IPC分类号： H04N19/50 ,  H03M7/30 ,  H04N19/102 ,  H04N19/146 ,  H04N19/423 ,  H04N19/70 ,  H04N7/12

    CPC分类号： H04N19/152 ,  H04N19/132 ,  H04N19/159 ,  H04N19/172 ,  H04N19/46 ,  H04N19/61

    摘要： To provide an image compression coding apparatus and method capable of minimizing a deterioration in picture quality which is caused on a reproduced image during an overflow of an output buffer. A picture top detector (7A) executes a picture top detection processing for discarding image compression data (S2) until a top of a picture of the image compression data (S2) is detected during detection of a start address, and restarts a normal operation after detecting the top of the picture. A processor (5) brings a detection start register (8) into a set state and causes the picture top detector (7A) to execute the picture top detection processing during an overflow of an output buffer (3a), and executes an interruption processing of rewriting, as a value of a write address register (9), an address where a top of an overflow picture to be a picture causing the overflow is stored.

    摘要翻译： 提供一种能够最小化在输出缓冲器溢出期间在再现图像上引起的图像质量劣化的图像压缩编码装置和方法。 图像顶部检测器（7A）执行用于丢弃图像压缩数据（S2）的图像顶部检测处理，直到在检测到开始地址期间检测到图像压缩数据（S 2）的图像的顶部，并重新开始 检测到图像顶部后的正常操作。 处理器（5）使检测开始寄存器（8）进入设置状态，并使图像顶部检测器（7A）在输出缓冲器（3a）溢出期间执行图像顶部检测处理，并执行中断 作为写入地址寄存器（9）的值的重写处理，存储溢出图像的顶部作为导致溢出的图像的地址。

    Semiconductor storage device with macro-cell with monitoring of input data
    5.
    发明授权
    Semiconductor storage device with macro-cell with monitoring of input data 失效
    具有监控输入数据的宏单元的半导体存储设备

    公开(公告)号：US5701267A

    公开(公告)日：1997-12-23

    申请号：US578892

    申请日：1995-12-27

    申请人： Shinichi Masuda ,  Satoshi Kumaki ,  Yoshinori Matsuura

    发明人： Shinichi Masuda ,  Satoshi Kumaki ,  Yoshinori Matsuura

    IPC分类号： G01R31/28 ,  G01R31/3185 ,  G11C7/00 ,  G11C29/00 ,  G11C29/14 ,  G11C29/22 ,  G11C29/56 ,  G11C13/00

    CPC分类号： G11C7/00 ,  G11C29/003

    摘要： It is an object of the present invention to realize bypass of input data in a macro-cell such as a FIFO memory etc. to facilitate test and evaluation about other macro-cells. A bypass route (6) is provided between an input port (DI) and an output port (DO) in a FIFO memory (1) and a data bypassing selector (8) is further provided for selecting the bypass route (6) and a sense amplifier (7) of a read bit line (R.BL). Then, in the test mode, a first selector control signal (S) is set to an L level and a second selector control signal (S) of opposite phase is set to an H level. Thus, in the test mode, a data inputted from the input port (DI) is outputted from the output port (DO) by way of the bypass route (6) without via memory cells (MC1-MCX).

    摘要翻译： 本发明的目的是实现诸如FIFO存储器等的宏小区中的输入数据的旁路，以便于关于其他宏小区的测试和评估。 旁路路径（6）设置在FIFO存储器（1）中的输入端口（DI）和输出端口（DO）之间，并且数据旁路选择器（8）还被设置用于选择旁路路径（6）和 读位线（RBL）的读出放大器（7）。 然后，在测试模式中，将第一选择器控制信号（S）设置为L电平，将相反相位的第二选择器控制信号（+ E，ovs S + EE）设置为H电平。 因此，在测试模式中，从输入端口（DI）输入的数据通过旁路路径（6）从输出端口（DO）输出，而不经由存储单元（MC1-MCX）输出。

    Data processor and data processing method reduced in power consumption during memory access
    6.
    发明授权
    Data processor and data processing method reduced in power consumption during memory access 失效
    数据处理器和数据处理方法降低了存储器访问期间的功耗

    公开(公告)号：US06918002B2

    公开(公告)日：2005-07-12

    申请号：US10053545

    申请日：2002-01-24

    申请人： Satoshi Kumaki ,  Tetsuya Matsumura ,  Hiroshi Segawa ,  Atsuo Hanami ,  Vasile Mosneaga

    发明人： Satoshi Kumaki ,  Tetsuya Matsumura ,  Hiroshi Segawa ,  Atsuo Hanami ,  Vasile Mosneaga

    IPC分类号： G06F1/26 ,  G06F1/32 ,  G06F12/00 ,  G06F12/04 ,  G06F13/42

    CPC分类号： G06F13/4239 ,  G11C7/1006 ,  G11C11/419 ,  Y02D10/14 ,  Y02D10/151

    摘要： When the CPU writes data into a memory, a 0 detection circuit detects the number of bits having the value 0 from the data. When the number of bits with 0 is equal to or larger than the number of bits with 1, the data output from the CPU is provided to the memory under control of a selector. When the number of bits with 0 is fewer than the number of bits with 1, the data output from the CPU is inverted and provided to the memory under control of the selector. Accordingly, the rewriting frequency of each memory cell from 0 to 1 or from 1 to 0 in the memory can be reduced in average. Thus the power consumption of the memory in a data writing mode can be reduced.

    摘要翻译： 当CPU将数据写入存储器时，0检测电路从数据中检测出具有值0的位数。 当具有0的比特数等于或大于具有1的比特数时，在选择器的控制下，从CPU输出的数据被提供给存储器。 当具有0的比特数少于具有1的比特数时，从CPU输出的数据被反转，并在选择器的控制下提供给存储器。 因此，可以平均地减少存储器中的每个存储单元从0到1或从1到0的重写频率。 因此，可以减少数据写入模式中的存储器的功耗。

    Program execution control device having addressability in accordance with M series pseudo-random number sequence
    8.
    发明授权
    Program execution control device having addressability in accordance with M series pseudo-random number sequence 失效
    具有符合M系列伪随机数序列的寻址能力的程序执行控制装置

    公开(公告)号：US5651123A

    公开(公告)日：1997-07-22

    申请号：US460947

    申请日：1995-06-05

    申请人： Shinichi Nakagawa ,  Kazuya Ishihara ,  Satoshi Kumaki ,  Atsuo Hanami ,  Hiroshi Segawa ,  Tetsuya Matsumura

    发明人： Shinichi Nakagawa ,  Kazuya Ishihara ,  Satoshi Kumaki ,  Atsuo Hanami ,  Hiroshi Segawa ,  Tetsuya Matsumura

    IPC分类号： G06F9/32 ,  G06F9/38 ,  G06F9/30

    CPC分类号： G06F9/3802 ,  G06F9/321 ,  G06F2207/7219

    摘要： Instructions of a program are stored at addresses sequentially designated in accordance with an M series pseudo-random number sequence in an instruction memory in the order of program addresses. A pseudo-random number program counter has a feedback shift register for generating the same M series pseudo-random number sequence and applies an address of an instruction to be read from the instruction memory to the instruction memory based on a generated pseudo-random number, and a jump address and a select signal from an instruction decoder. As a result, instructions are read from the instruction memory and executed in the order of program addresses. The feedback shift register can be implemented as a small-scale circuit and operable at high speed.

    摘要翻译： 程序的指令按照程序地址的顺序存储在指令存储器中根据M系列伪随机数序列顺序指定的地址处。 伪随机数程序计数器具有用于产生相同M系列伪随机数序列的反馈移位寄存器，并且基于生成的伪随机数将从指令存储器读出的指令的地址应用于指令存储器， 以及来自指令解码器的跳转地址和选择信号。 结果，从指令存储器中读取指令并按程序地址的顺序执行。 反馈移位寄存器可以实现为小规模电路并且可以高速运行。

    Motion vector detecting device improved in detection speed of motion vectors and system employing the same devices
    9.
    发明授权
    Motion vector detecting device improved in detection speed of motion vectors and system employing the same devices 失效
    运动矢量检测装置提高运动矢量的检测速度和采用相同装置的系统

    公开(公告)号：US06968011B2

    公开(公告)日：2005-11-22

    申请号：US10155993

    申请日：2002-05-29

    申请人： Satoshi Kumaki ,  Tetsuya Matsumura ,  Atsuo Hanami ,  Yoshinori Matsuura

    发明人： Satoshi Kumaki ,  Tetsuya Matsumura ,  Atsuo Hanami ,  Yoshinori Matsuura

    IPC分类号： H04N19/50 ,  H04N5/14 ,  H04N19/503 ,  H04N19/543 ,  H04N19/57 ,  H04N7/12

    CPC分类号： H04N5/145 ,  H04N19/436 ,  H04N19/51

    摘要： The control circuit controls output of template block data held in the input section such that a plurality of operation units within the operation section are provided with data of unadjacent template blocks that are different from each other. The operation units within the operation section detect motion vectors according to the template block data provided thereto. Thus, motion vector detection in the template blocks except for those in a region on a display screen requiring no motion vector detection is distributed in the plurality of operation units. Accordingly, the motion vector search can be performed in a wider range in a vertical or horizontal direction than in the conventional case within the same operation time.

    摘要翻译： 控制电路控制保持在输入部分中的模板块数据的输出，使得操作部分内的多个操作单元被提供有彼此不同的不相邻模板块的数据。 操作部分内的操作单元根据提供给它的模板块数据来检测运动矢量。 因此，除了不需要运动矢量检测的显示画面上的区域中的模板块中的运动矢量检测分布在多个运算单元中。 因此，在相同的动作时间内，与现有的情况相比，可以在比垂直方向或水平方向更宽的范围内进行运动矢量搜索。

    Encoding device mounted on one chip for multiplexing video signal and audio signal
    10.
    发明授权
    Encoding device mounted on one chip for multiplexing video signal and audio signal 有权
    编码装置安装在一个芯片上，用于复用视频信号和音频信号

    公开(公告)号：US06765961B2

    公开(公告)日：2004-07-20

    申请号：US09814092

    申请日：2001-03-22

    申请人： Hiroshi Segawa ,  Satoshi Kumaki

    发明人： Hiroshi Segawa ,  Satoshi Kumaki

    IPC分类号： H04N712

    CPC分类号： H04N21/2368 ,  H04N21/4341

    摘要： An encoding device includes a processor unit controlling an overall operation and at the same time having a software for executing an audio encoding process, a video encoding unit to execute a video encoding process, a multiplex process unit to execute a system process and a timing control unit to generate a timing signal for activating an audio encoding process, a video encoding process and a system process, all of these elements are mountable on the same substrate. Each of a control process for controlling the audio encoding process, the video encoding process and system process is executed as an interrupt process. The processor unit includes an interrupt control circuit. The interrupt control circuit selects, based on a predetermined priority, one interrupt process corresponding to at least one generated timing signal.

    摘要翻译： 一种编码装置，包括控制整个操作并且同时具有执行音频编码处理的软件的处理器单元，执行视频编码处理的视频编码单元，执行系统处理和定时控制的多路复用处理单元 单元以产生用于激活音频编码处理，视频编码处理和系统处理的定时信号，所有这些元素可安装在同一基板上。 作为中断处理，执行用于控制音频编码处理，视频编码处理和系统处理的控制处理。 处理器单元包括一个中断控制电路。 中断控制电路基于预定的优先级选择与至少一个产生的定时信号相对应的一个中断处理。