摘要:
A wide-bit output semiconductor storage device of high speed and low noise is provided in which output circuits are grouped into two groups and the two output circuit groups are so controlled as to be switched in directions of levels which are opposite to each other.
摘要:
An improved buffer circuit arrangement is provided which is particularly useful for semiconductor integrated circuit semiconductor memories and microprocessors. The buffer circuit is capable of switching large loads in various types of LSIs, and features a low noise and high speed circuit operation. This is accomplished by a parallel connection of output transistors in an output buffer circuit, and by differentiating the starting time of operation between the output transistors connected in parallel without using a delay circuit. For example, differentiating the starting times can be achieved by either providing the transistors with different characteristics from one another or the driving circuits with different characteristics from one another. Another aspect of the circuit is the provision of a two-level preset arrangement which presets the output node of the circuit to predetermined values before the input signals are applied.
摘要:
A semiconductor memory device which includes at least one of (1) an input buffer circuit which generates internal address signals in response to an incoming address; (2) a decoder circuit formed of plural logic gates each of which is composed of the combination of MOS and bipolar circuitry; (3) a sense amplifier circuit including a multiemitter transistor; (4) a signal or address transition detector circuit which includes input circuits each receiving, for example, an address signal of a voltage amplitude and outputting a current amplitude signal in response to a change in level of the address signal, and a detector circuit connected thereto which has a cascode amplifier arranged such that it receives current amplitude signals at an input thereof and in which the cascode amplifier input is maintained at a substantially constant voltage, in which the detection circuit detects a transition of one or more of the current amplitude signals and, in response thereto, generates an ATD signal of a voltage amplitude; and (5) an output buffer circuit, in which the decoder, sense amplifier and output buffer of the device are controlled in accordance with signals from a clock generator, which is responsive to the ATD signal.
摘要:
An improved buffer circuit arrangement is provided which is particularly useful for semiconductor integrated circuit semiconductor memories and microprocessors. The buffer circuit is capable of switching large loads in various types of LSIs, and features a low noise and high speed circuit operation. This is accomplished by a parallel connection of output transistors in an output buffer circuit, and by differentiating the starting time of operation between the output transistors connected in parallel without using a delay circuit. For example, differentiating the starting times can be achieved by either providing the transistors with different characteristics from one another or the driving circuits with different characteristics from one another. Another aspect of the circuit is the provision of a two-level preset arrangement which presets the output node of the circuit to predetermined values before the input signals are applied.
摘要:
A semiconductor device which includes at least one of (1) an input buffer circuit formed of an input level converter and a non-inverting buffer circuit and an inverting buffer circuit each including BiCMOS circuitry which effects high-speed operation; (2) a decoder circuit formed of plural logic gates each of which is composed of the combination of MOS and bipolar circuitry; (3) a sense amplifier circuit including a multiemitter transistor; (4) a signal or address transition detector circuit which includes input circuits each receiving, for example, an address signal of a voltage amplitude and outputting a current amplitude signal in response to a change in level of the address signal, and a detector circuit connected thereto which has a cascode amplifier arranged such that it receives current amplitude signals at an input thereof and in which the cascode amplifier input is maintained at a substantially constant voltage, in which the detection circuit detects a transition of one or more of the current amplitude signals and, in response thereto, generates an ATD signal of a voltage amplitude; and (5) an output buffer circuit, in which the decoder, sense amplifier and output buffer of the device such as for a memory are controlled in accordance with signals from a clock generator, which is responsive to the ATD signal.
摘要:
An input buffer for processing an external signal is provided in one of passways, which is the most closest to a line for equally dividing the whole of a plurality of memory cell blocks longitudinally or laterally into two sections, the passway interposing between the adjacent memory cell blocks of the plurality of memory cell blocks to which a processed signal of the input buffer is transmitted, whereby the length of the signal pass from the input buffer to each memory cell of the memory cell blocks can be shortened. Therefore, since the memory cell or a logic element existing between the input buffer and the memory cell is operated by a pulse of little distortion without delay of time, a access time can be reduced and a processing speed of a microprocessor can be increased. Further, a degree of freedom in designing a system of a memory or the microprocessor is further improved.
摘要:
A semiconductor device is provided which comprises a memory mat formed by dividing a memory into a plurality of blocks and a circuit arrangement disposed at every memory mat block for generating access suppression signals at least for defective memory cells within that block. Using this arrangement, the access speed to a redundant memory cell array for relieving the defects is increased so that a semiconductor memory device capable of a high speed operation is obtained.
摘要:
An arrangement which is particularly effective for decoders in semiconductor memory circuits which use, for example, common NMOS to receive one input for a plurality of logic decoder gates is provided includes a plurality of logic gates each having a first input terminal for respectively receiving first input signals and each being coupled to a common node. In one embodiment, first and second switching elements are also coupled to the common node. The first and second switching elements are both coupled to a second input terminal for receiving a second input signal which is common to the plurality of logic gates, and both operate complementary to one another in response to the second input signal. An improved read/write arrangement is also provided for such semiconductor memory circuit which includes circuitry to prevent connection of a common read line to the data lines during the writing operation. This enhances the writing speed by removing the load of the common read line during writing.
摘要:
A generator having a field coil L, and an SW1 control circuit 2 for controlling field current flowing through the field coil L. When a generating operation of the generator is to be ended, a switch 1 SW1 is turned off to interrupt the field current flowing through the field coil L, and a switch 2 SW2 is turned off to allow the field current remaining the field coil L to the current path including a resistance element 1 with a resistance element capable of quickly attenuating the field current.
摘要:
A semiconductor memory comprises a write driver which is provided to correspond to respective data line and by which data lines connected with a memory cell through the control of a word line are driven in a write operation. The write driver includes MOSFETs of first group and MOSFETs of second group. In a case where a write enable signal does not designate the write operation, the MOSFETs of the first group are normally in ON states to pull up the data lines. Besides, in a case where the write enable signal designates the write operation, each of them operates in accordance with the value of input data, to maintain the ON states and pull up the corresponding data line in case of driving the data line to a "high" level and to fall into OFF states in case of driving the data line to a "low" level. On the other hand, the MOSFETs of the second group are normally in OFF states. Besides, in the case where the write enable signal designates the write operation, each of them operates in accordance with the value of the input data, to fall into ON state and draw the corresponding data line to the low level in the case of driving the data lines to the low level.