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公开(公告)号：US20170018501A1
公开(公告)日：2017-01-19
申请号：US14929309
申请日：2015-10-31
Inventor： Marshall Maple , Ashish Alawani , Li Sun , Sarah Haney , Lea-Teng Lee , Wei Yao
IPC: H01L23/528 , H01L29/778 , H01L29/20 , H01L29/737 , H01L23/522 , H01L21/768
CPC classification number: H01L23/5283 , H01L21/76804 , H01L21/76816 , H01L21/76877 , H01L23/3736 , H01L23/5226 , H01L29/20 , H01L29/737 , H01L29/7786
Abstract: An apparatus, a semiconductor package including the apparatus and a method are disclosed. The apparatus includes a substrate, pluralities of vias disposed in the substrate. The vias are disposed in a hexagonal arrangement.
Abstract translation: 公开了一种装置，包括该装置的半导体封装和方法。 该装置包括基板，多个通孔设置在基板中。 通孔以六边形排列。
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2.发明申请PRINTED CIRCUIT BOARD COMPRISING CO-PLANAR SURFACE PADS AND INSULATING DIELECTRIC 审中-公开印制电路板，包括平面表面和绝缘介质公开(公告)号：US20150351229A1
公开(公告)日：2015-12-03
申请号：US14289098
申请日：2014-05-28
Inventor： Lea-Teng Lee , Sarah Haney
CPC classification number: H05K1/0268 , H05K2201/09881 , H05K2201/09909 , H05K2203/0353 , H05K2203/0588
Abstract: A printed circuit board (PCB) comprises a non-conductive base layer, a conductive interconnect disposed on the non-conductive base layer and comprising at least two surface pads separated by a trench, and a insulating dam disposed in the trench, wherein the insulating dam electrically isolates the at least two surface pads and has an upper surface that is substantially co-planar with respective upper surfaces of the at least two surface pads.
Abstract translation: 印刷电路板（PCB）包括非导电基底层，布置在非导电基底层上的导电互连，并且包括由沟槽分隔开的至少两个表面焊盘和设置在沟槽中的绝缘堤坝，其中绝缘 坝至少两个表面焊盘电隔离，并且具有与至少两个表面焊盘的相应上表面基本共面的上表面。
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3.发明申请公开(公告)号：US20170301559A1
公开(公告)日：2017-10-19
申请号：US15130202
申请日：2016-04-15
Inventor： Wei-Shun Wang , Li Sun , Ashish Alawani , Lea-Teng Lee
CPC classification number: H01L21/4853 , H01L21/4864 , H01L23/3121 , H01L24/81 , H01L25/0655 , H01L25/16 , H01L25/50 , H01L2021/6009 , H01L2021/60135 , H01L2021/6024 , H01L2224/0401 , H01L2224/81024 , H01L2224/81192 , H01L2224/81193 , H01L2224/81815 , H01L2924/19105
Abstract: A method is provided for attaching components to pads on a PCB, where total accumulated tolerances are reduced by separating accumulated tolerances into multiple processes. The method includes performing first and second processes having first and second accumulated tolerances, respectively. The first process includes placing a first stencil over the PCB, the first stencil defining first apertures corresponding to the pads; printing solder paste onto the pads using the first stencil; and reflowing the printed solder paste to form corresponding solder bumps on the pads. The second process includes placing a second stencil over the PCB, the second stencil defining second apertures corresponding to the pads; printing flux onto the solder bumps using the second stencil; placing at least one component on the printed flux; and reflowing the printed flux and the solder bumps to form corresponding solder joints between the at least one component and the first pads, respectively.
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Patent Agency Ranking
公开(公告)号：US20170215278A1
公开(公告)日：2017-07-27
申请号：US15008137
申请日：2016-01-27
Inventor： Padam Jain , Sarah Haney , Lea-Teng Lee
CPC classification number: H05K1/0353 , H05K3/4682 , H05K2201/0195
Abstract: A coreless substrate of a printed circuit board is provided. The coreless substrate includes a first outer metal layer; a first primer layer formed on the first outer metal layer; a first layer of functional prepreg material formed on the first primer layer; a second primer layer formed over the first layer of functional prepreg material; and a second outer metal layer formed on the second primer layer. The first outer metal layer corresponds to a first outer most surface of the printed circuit board, and the second outer metal layer corresponds to a second outer most surface of the printed circuit board.
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公开(公告)号：US09668340B1
公开(公告)日：2017-05-30
申请号：US15139122
申请日：2016-04-26
Inventor： Jack Ajoian , Lea-Teng Lee
CPC classification number: H05K1/0298 , H05K1/09 , H05K3/243 , H05K3/4007 , H05K2201/0338 , H05K2201/0376
Abstract: A build-up process for fabricating a multi-layer PCB is provided that prevents, or at least reduces the lengths of, overhangs in the finishing metal layer that is plated onto the electrical contact metal layer. The metal seed layer is etched away prior to plating the finishing metal layer onto the electrical contact metal layer. The electrical contact metal layer is covered with a layer of dielectric material, which is then patterned to selectively expose preselected areas of the electrical contact metal layer. The exposed preselected areas of the electrical contact metal layer are then plated with the finishing layer of metal. The result is that overhangs are eliminated or at least greatly reduced in length. In addition, the dielectric material layer serves a function similar to that of a solder mask and obviates the need to apply the oxide to serve as a solder mask.
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公开(公告)号：US09974181B2
公开(公告)日：2018-05-15
申请号：US15079070
申请日：2016-03-24
Inventor： Sarah Haney , Deog Soon Choi , Hyun Mo Ku , Lea-Teng Lee , Nitesh Kumbhat , Ah Ron Lee
IPC: H05K7/00 , H05K1/18 , H05K1/11 , H01L23/552 , H01L25/065
CPC classification number: H05K1/181 , H01L23/552 , H01L25/0655 , H01L2224/16225 , H01L2224/48091 , H01L2224/73257 , H01L2924/00014 , H01L2924/15321 , H01L2924/15322 , H01L2924/15323 , H01L2924/3025 , H05K1/0218 , H05K1/111 , H05K3/0052 , H05K3/284 , H05K2201/0317 , H05K2201/0715 , H05K2201/09354 , H05K2201/09909 , H05K2201/10371 , H01L2224/45099
Abstract: A module includes a printed circuit board (PCB) having a substrate, component pads on a top surface of the substrate, and contact pads formed on a bottom surface of the substrate. The module further includes a mold compound disposed over the PCB; an external shield disposed over a top surface of the mold compound and on side surfaces of the mold compound and the PCB, where the external shield is configured to provide shielding of at least one component connected to at least one component pad from electromagnetic radiation; and a back-spill barrier formed on the bottom of the substrate. The back-spill barrier surrounds the contact pads, and is configured to prevent the external shield from making contact with the contact pads.
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7.发明授权公开(公告)号：US09865479B2
公开(公告)日：2018-01-09
申请号：US15130202
申请日：2016-04-15
Inventor： Wei-Shun Wang , Li Sun , Ashish Alawani , Lea-Teng Lee
CPC classification number: H01L21/4853 , H01L21/4864 , H01L23/3121 , H01L24/81 , H01L25/0655 , H01L25/16 , H01L25/50 , H01L2021/6009 , H01L2021/60135 , H01L2021/6024 , H01L2224/0401 , H01L2224/81024 , H01L2224/81192 , H01L2224/81193 , H01L2224/81815 , H01L2924/19105
Abstract: A method is provided for attaching components to pads on a PCB, where total accumulated tolerances are reduced by separating accumulated tolerances into multiple processes. The method includes performing first and second processes having first and second accumulated tolerances, respectively. The first process includes placing a first stencil over the PCB, the first stencil defining first apertures corresponding to the pads; printing solder paste onto the pads using the first stencil; and reflowing the printed solder paste to form corresponding solder bumps on the pads. The second process includes placing a second stencil over the PCB, the second stencil defining second apertures corresponding to the pads; printing flux onto the solder bumps using the second stencil; placing at least one component on the printed flux; and reflowing the printed flux and the solder bumps to form corresponding solder joints between the at least one component and the first pads, respectively.
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公开(公告)号：US20170280561A1
公开(公告)日：2017-09-28
申请号：US15079070
申请日：2016-03-24
Inventor： Sarah Haney , Deog Soon Choi , Hyun Mo Ku , Lea-Teng Lee , Nitesh Kumbhat , Ah Ron Lee
IPC: H05K1/18 , H05K1/11 , H01L23/31 , H05K1/09 , H01L23/00 , H01L25/065 , H01L25/16 , H01L23/498 , H01L23/552
CPC classification number: H05K1/181 , H01L23/552 , H01L25/0655 , H01L2224/16225 , H01L2224/48091 , H01L2224/73257 , H01L2924/00014 , H01L2924/15321 , H01L2924/15322 , H01L2924/15323 , H01L2924/3025 , H05K1/0218 , H05K1/111 , H05K3/0052 , H05K3/284 , H05K2201/0317 , H05K2201/0715 , H05K2201/09354 , H05K2201/09909 , H05K2201/10371 , H01L2224/45099
Abstract: A module includes a printed circuit board (PCB) having a substrate, component pads on a top surface of the substrate, and contact pads formed on a bottom surface of the substrate. The module further includes a mold compound disposed over the PCB; an external shield disposed over a top surface of the mold compound and on side surfaces of the mold compound and the PCB, where the external shield is configured to provide shielding of at least one component connected to at least one component pad from electromagnetic radiation; and a back-spill barrier formed on the bottom of the substrate. The back-spill barrier surrounds the contact pads, and is configured to prevent the external shield from making contact with the contact pads.
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