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公开(公告)号：US09668340B1
公开(公告)日：2017-05-30
申请号：US15139122
申请日：2016-04-26
Inventor： Jack Ajoian , Lea-Teng Lee
CPC classification number: H05K1/0298 , H05K1/09 , H05K3/243 , H05K3/4007 , H05K2201/0338 , H05K2201/0376
Abstract: A build-up process for fabricating a multi-layer PCB is provided that prevents, or at least reduces the lengths of, overhangs in the finishing metal layer that is plated onto the electrical contact metal layer. The metal seed layer is etched away prior to plating the finishing metal layer onto the electrical contact metal layer. The electrical contact metal layer is covered with a layer of dielectric material, which is then patterned to selectively expose preselected areas of the electrical contact metal layer. The exposed preselected areas of the electrical contact metal layer are then plated with the finishing layer of metal. The result is that overhangs are eliminated or at least greatly reduced in length. In addition, the dielectric material layer serves a function similar to that of a solder mask and obviates the need to apply the oxide to serve as a solder mask.
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2.发明授权Method of fabricating printed circuit board (PCB) substrate having a cavity 有权制造具有空腔的印刷电路板（PCB）基板的方法公开(公告)号：US09085826B2
公开(公告)日：2015-07-21
申请号：US14039784
申请日：2013-09-27
Inventor： Jack Ajoian
IPC: C23F1/02
CPC classification number: C23F1/02 , C23F4/04 , H01L2224/16225 , H01L2224/32145 , H01L2224/73265 , H05K3/0038 , H05K3/4697 , H05K2203/107
Abstract: A method is provided for fabricating a substrate having multiple metal layers separated by one or more dielectric layers, respectively. The method includes forming a cavity in at least one dielectric layer through an exposed portion of a top dielectric layer of the substrate, applying metal to side and bottom surfaces of the cavity, forming a pattern through a portion of the metal applied to the bottom surface of the cavity, and micro-etching the metal applied to the bottom surface of the cavity. The micro-etching extends the pattern through a remaining portion of the metal applied to the bottom surface of the cavity.
Abstract translation: 提供了一种用于制造分别由一个或多个电介质层分隔的多个金属层的衬底的方法。 该方法包括通过衬底的顶部介电层的暴露部分在至少一个电介质层中形成空腔，将金属施加到空腔的侧表面和底表面，通过施加到底表面的金属的一部分形成图案 并且微蚀刻施加到腔的底表面的金属。 微蚀刻通过施加到腔的底表面的金属的剩余部分延伸图案。
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公开(公告)号：US20180063951A1
公开(公告)日：2018-03-01
申请号：US15251230
申请日：2016-08-30
Inventor： Nitesh Kumbhat , Li Sun , Aaron Lee , Deog-Soon Choi , Hyun-Mo Ku , Jack Ajoian
CPC classification number: H05K1/111 , H05K1/0271 , H05K1/0373 , H05K1/185 , H05K3/0014 , H05K9/0081 , H05K2201/068 , H05K2201/10977
Abstract: A process for forming an encapsulating mold compound into a molded solder mask on a bottom surface of a PCB is provided that allows the molded solder mask to have a very precise, preselected thickness, or height, while also ensuring that no gaps between the solder mask and side walls of the electrical contact pads exist. A circuit board and circuit board assembly that incorporate the molded solder mask are also provided. The molded solder mask is fabricated in such a way that overlap between the molded solder mask and the electrical contact pads and gaps between the molded solder mask and the side walls of the electrical contact pads are avoided. In addition, the molded solder mask allows the pitch between adjacent electrical contact pads to be greatly reduced compared to the pitch that is possible using a traditional solder mask formed by the traditional photolithographic approach.
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Patent Agency Ranking
公开(公告)号：US09907169B1
公开(公告)日：2018-02-27
申请号：US15251230
申请日：2016-08-30
Inventor： Nitesh Kumbhat , Li Sun , Aaron Lee , Deog-Soon Choi , Hyun-Mo Ku , Jack Ajoian
CPC classification number: H05K1/111 , H05K1/0271 , H05K1/0373 , H05K1/185 , H05K3/0014 , H05K9/0081 , H05K2201/068 , H05K2201/10977
Abstract: A process for forming an encapsulating mold compound into a molded solder mask on a bottom surface of a PCB is provided that allows the molded solder mask to have a very precise, preselected thickness, or height, while also ensuring that no gaps between the solder mask and side walls of the electrical contact pads exist. A circuit board and circuit board assembly that incorporate the molded solder mask are also provided. The molded solder mask is fabricated in such a way that overlap between the molded solder mask and the electrical contact pads and gaps between the molded solder mask and the side walls of the electrical contact pads are avoided. In addition, the molded solder mask allows the pitch between adjacent electrical contact pads to be greatly reduced compared to the pitch that is possible using a traditional solder mask formed by the traditional photolithographic approach.
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公开(公告)号：US09832865B2
公开(公告)日：2017-11-28
申请号：US15138309
申请日：2016-04-26
Inventor： Jack Ajoian , Padam Jain
CPC classification number: H05K3/4673 , H05K1/0224 , H05K3/0038 , H05K3/4685 , H05K3/4688 , H05K3/4694 , H05K2201/0187 , H05K2203/0514 , H05K2203/107
Abstract: A build-up process for fabricating a multi-layer PCB is provided during which a mezzanine redistribution, or routing, structure is formed within one of the PCB dielectric material layers that allows additional electrical interconnections (i.e., traces and crossovers) to be made within that layer, thereby obviating the need to add an additional PCB layer in order to make those interconnections. The mezzanine redistribution structure also can be interconnected with the metal layers that are above and below it to further increase routing complexity and flexibility. The mezzanine redistribution structure can be formed without increasing the total thickness of the PCB and without substantially increasing costs.
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公开(公告)号：US20170311444A1
公开(公告)日：2017-10-26
申请号：US15138309
申请日：2016-04-26
Inventor： Jack Ajoian , Padam Jain
CPC classification number: H05K3/4673 , H05K1/0224 , H05K3/0038 , H05K3/4685 , H05K3/4688 , H05K3/4694 , H05K2201/0187 , H05K2203/0514 , H05K2203/107
Abstract: A build-up process for fabricating a multi-layer PCB is provided during which a mezzanine redistribution, or routing, structure is formed within one of the PCB dielectric material layers that allows additional electrical interconnections (i.e., traces and crossovers) to be made within that layer, thereby obviating the need to add an additional PCB layer in order to make those interconnections. The mezzanine redistribution structure also can be interconnected with the metal layers that are above and below it to further increase routing complexity and flexibility. The mezzanine redistribution structure can be formed without increasing the total thickness of the PCB and without substantially increasing costs.
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7.发明申请ELECTRONIC MODULE HAVING AN OXIDE SURFACE FINISH AS A SOLDER MASK, AND METHOD OF MANUFACTURING ELECTRONIC MODULE USING ORGANIC SOLDERABILITY PRESERVATIVE AND OXIDE SURFACE FINISH PROCESSES 审中-公开具有作为焊接掩模的氧化物表面的电子模块，以及使用有机可焊性保护和氧化物表面处理工艺制造电子模块的方法公开(公告)号：US20160064252A1
公开(公告)日：2016-03-03
申请号：US14471733
申请日：2014-08-28
Inventor： Jack Ajoian
IPC: H01L21/48 , H01L21/56 , H01L23/495
CPC classification number: H01L23/49827 , H01L21/486 , H01L23/3121 , H01L23/49822 , H01L23/49838 , H01L23/49894 , H01L24/81 , H01L2021/60015 , H01L2224/13111 , H01L2224/13147 , H01L2224/16227 , H01L2224/81011 , H01L2224/81024 , H01L2224/81193 , H01L2924/181 , H05K3/282 , H05K3/284 , H05K3/3436 , H05K3/3452 , H05K2201/10719 , H05K2201/10734 , H05K2203/121 , H05K2203/1316 , H05K2203/1327 , H01L2924/00012 , H01L2924/014 , H01L2924/00014
Abstract: An electronic module includes a substrate, conductive pads at top and bottom surfaces of the substrate, at least one electronic component disposed on the top surface of the substrate and soldered to the pads at the top surface of the substrate, a molding compound covering the at least one electronic component, and a solder resist comprising an organo-metallic compound at regions between respective ones of the pads at the bottom surface of the substrate. The module is manufactured using both an OSP surface finishing process to coat the pads at the top surface of the substrate with OSP so as to protect the pads from oxidation while the electronic component is being connected to the substrate, and an oxide surface finish process to form the solder resist.
Abstract translation: 电子模块包括基板，在基板的顶表面和底表面处的导电焊盘，至少一个电子部件，其设置在基板的顶表面上并焊接到基板的顶表面上的焊盘;覆盖在基板上的模塑料 至少一个电子部件，以及包含有机金属化合物的焊料抗蚀剂，其位于衬底底表面的相应焊盘之间的区域。 该模块使用OSP表面处理工艺制造，以用OSP涂覆在基板的顶表面上的焊盘，以便在电子部件连接到基板时保护焊盘免受氧化，并且氧化物表面光洁度处理 形成阻焊剂。
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8.发明申请公开(公告)号：US20150090688A1
公开(公告)日：2015-04-02
申请号：US14039784
申请日：2013-09-27
Inventor： Jack Ajoian
IPC: C23F1/02
CPC classification number: C23F1/02 , C23F4/04 , H01L2224/16225 , H01L2224/32145 , H01L2224/73265 , H05K3/0038 , H05K3/4697 , H05K2203/107
Abstract: A method is provided for fabricating a substrate having multiple metal layers separated by one or more dielectric layers, respectively. The method includes forming a cavity in at least one dielectric layer through an exposed portion of a top dielectric layer of the substrate, applying metal to side and bottom surfaces of the cavity, forming a pattern through a portion of the metal applied to the bottom surface of the cavity, and micro-etching the metal applied to the bottom surface of the cavity. The micro-etching extends the pattern through a remaining portion of the metal applied to the bottom surface of the cavity.
Abstract translation: 提供了一种用于制造分别由一个或多个电介质层分隔的多个金属层的衬底的方法。 该方法包括通过衬底的顶部介电层的暴露部分在至少一个电介质层中形成空腔，将金属施加到空腔的侧表面和底表面，通过施加到底表面的金属的一部分形成图案 并且微蚀刻施加到腔的底表面的金属。 微蚀刻通过施加到腔的底表面的金属的剩余部分延伸图案。
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