公开(公告)号：US5324690A

公开(公告)日：1994-06-28

申请号：US11919

申请日：1993-02-01

申请人： Avgerinos V. Gelatos ,  Stephen S. Poon

发明人： Avgerinos V. Gelatos ,  Stephen S. Poon

IPC分类号： B24B37/04 ,  C23C16/34 ,  H01L21/3105 ,  H01L21/314 ,  H01L21/318 ,  H01L23/532 ,  H01L21/304

CPC分类号： B24B37/042 ,  C23C16/342 ,  H01L21/31053 ,  H01L21/3144 ,  H01L21/318 ,  H01L23/5329 ,  H01L2924/0002 ,  Y10S148/113 ,  Y10S438/97

摘要： A non-silyated, ternary boron nitride film (18, 38) is provided for semiconductor device applications. The non-silyated, ternary boron nitride film is preferably formed by plasma-enhanced chemical vapor deposition using non-silyated compounds of boron, nitrogen, and either oxygen, germanium, germanium oxide, fluorine, or carbon. In one embodiment, boron oxynitride (BNO) is deposited in a plasma-enhanced chemical vapor deposition reactor using ammonia (NH.sub.3), diborane (B.sub.2 H.sub.6), and nitrous oxide (N.sub.2 O). The BNO film has a dielectric constant of about 3.3 and exhibits a negligible removal rate in a commercial polishing apparatus. Because of its low dielectric constant and high hardness, the ternary boron nitride film formed in accordance with the invention can be advantageously used as a polish-stop layer and as a interlevel dielectric layer in a semiconductor device.

摘要翻译： 为半导体器件应用提供了不含硅酸盐的三元氮化硼膜（18,38）。 非硅化三元氮化硼膜优选通过使用硼，氮和氧，锗，氧化锗，氟或碳的非硅化化合物的等离子体增强化学气相沉积来形成。 在一个实施方案中，使用氨（NH 3），乙硼烷（B 2 H 6）和一氧化二氮（N 2 O）在等离子体增强化学气相沉积反应器中沉积氮氧化硼（BNO）。 BNO膜的介电常数约为3.3，在商业抛光装置中的去除率可忽略不计。 由于其低介电常数和高硬度，根据本发明形成的三元氮化硼膜可以有利地用作半导体器件中的抛光停止层和层间电介质层。

公开(公告)号：US5064683A

公开(公告)日：1991-11-12

申请号：US604855

申请日：1990-10-29

申请人： Stephen S. Poon ,  Avgerinos V. Gelatos

发明人： Stephen S. Poon ,  Avgerinos V. Gelatos

IPC分类号： H01L21/02 ,  H01L21/3105 ,  H01L21/321

CPC分类号： H01L21/31053 ,  H01L21/02065 ,  H01L21/02074 ,  H01L21/3212

摘要： In a polish palnarization process using a polishing apparatus and an abrasive slurry, a boron nitride (BN) polish stop layer (18) is provided to increase the polish selectivity. The BN layer deposited in accordance with the invention has a hexagonal-close-pack crystal orientation and is characterized by chemical inertness and high hardness. The BN layer has a negligible polish removal rate yielding extremely high polish selectivity when used as a polish stop for polishing a number of materials commonly used in the fabrication of semiconductor devices. In accordance with the invention, a substrate (12) is provided having an uneven topography including elevated regions and recessed regions. A BN polish stop layer (18) is desposited to overlie the substrate (12) and a fill material (20, 36) which can be dielectric material or a conductive material, is deposited to overlie the BN polish stop (18) and the recessed regions of the substrate. The fill material is then polished back until the BN polish stop is reached resulting in the formation of a planar surface (38).

摘要翻译： 在使用抛光装置和磨料浆料的抛光法制法中，提供了氮化硼（BN）抛光停止层（18）以提高抛光选择性。 根据本发明沉积的BN层具有六方密封组合晶体取向，其特征在于化学惰性和高硬度。 当用作抛光通常用于制造半导体器件的许多材料的抛光停止时，BN层具有可忽略的抛光除去率，产生极高的抛光选择性。 根据本发明，提供了具有包括升高区域和凹陷区域的不平坦形貌的基板（12）。 BN抛光停止层（18）被布置成覆盖在基板（12）上，并且可以沉积可以是电介质材料或导电材料的填充材料（20,36）以覆盖在BN抛光止挡（18）上并且凹陷 基底的区域。 然后将填充材料抛光回直到达到BN抛光止挡，从而形成平坦表面（38）。

公开(公告)号：US4753898A

公开(公告)日：1988-06-28

申请号：US71002

申请日：1987-07-09

申请人： Louis C. Parrillo ,  Stephen S. Poon

发明人： Louis C. Parrillo ,  Stephen S. Poon

IPC分类号： H01L21/8238 ,  H01L27/092 ,  H01L21/265

CPC分类号： H01L21/823864 ,  H01L27/0928

摘要： A process is disclosed for fabricating LDD CMOS structures having a reduced mask count and improved manufacturability. In one embodiment of the invention a CMOS structure is formed having gate insulators overlying N and P type surface regions. Gate electrodes are formed on each of the surface regions and a spacer forming material is deposited over the electrodes and the surface regions. The spacer material is anisotropically etched from one of the surface regions to form spacers at the edge of the first gate electrode while retaining the spacer forming material over the second surface region. Source and drain regions of the first MOS transistor are implanted using the spacers as an implantation mask. The spacers are removed and a lightly doped source and drain is implanted using the gate electrode as a mask. The implanted source and drain regions are oxidized using the remaining spacer forming material as an oxidation mask to prevent oxidation of the second surface region. Devices are then fabricated in that second surface region by implanting devices of opposite conductivity type either with or without the formation of spacers and an LDD structure on the devices of second conductivity type.

摘要翻译： 公开了一种用于制造具有减小的掩模计数和改进的可制造性的LDD CMOS结构的工艺。 在本发明的一个实施例中，形成了具有覆盖N和P型表面区域的栅极绝缘体的CMOS结构。 在每个表面区域上形成栅电极，并且在电极和表面区域上沉积间隔物形成材料。 间隔物材料从一个表面区域被各向异性地蚀刻，以在第一栅电极的边缘处形成间隔物，同时将间隔物形成材料保持在第二表面区域上。 使用间隔物作为注入掩模注入第一MOS晶体管的源极和漏极区域。 去除间隔物，并使用栅电极作为掩模注入轻掺杂的源极和漏极。 使用剩余的间隔物形成材料作为氧化掩模来氧化注入的源区和漏区，以防止第二表面区的氧化。 然后通过在具有第二导电类型的器件上形成间隔物和LDD结构的情况下注入相反导电类型的器件，在该第二表面区域中制造器件。

公开(公告)号：US20130021289A1

公开(公告)日：2013-01-24

申请号：US13186238

申请日：2011-07-19

申请人： Wei Chen ,  Steven P. Hotelling ,  John Z. Zhong ,  Shih-Chang Chang ,  Stephen S. Poon

发明人： Wei Chen ,  Steven P. Hotelling ,  John Z. Zhong ,  Shih-Chang Chang ,  Stephen S. Poon

IPC分类号： G06F3/044

CPC分类号： G06F3/044 ,  G06F1/1601 ,  G06F1/1643 ,  G06F3/0412 ,  G06F3/0416 ,  G06F3/047 ,  G06F3/04886 ,  G06F2203/04112 ,  H01L27/323 ,  H01L27/3276 ,  H01L27/3288 ,  H01L27/3293 ,  H01L51/5237 ,  H01L51/5246 ,  H01L51/5253 ,  H01L51/5281 ,  H01L51/5284 ,  H01L2251/5338

摘要： Displays such as organic light-emitting diode displays may be provided with touch sensing capabilities. A touch sensor may be formed from electrodes located on a thin-film encapsulation layer or one or more sides of a polarizer. A single-sided or double-sided touch sensor panel may be attached to the upper or lower surface of a polarizer. Control circuitry may be used to provide control signals to light-emitting diodes in the display using a grid of control lines. The control lines and transparent electrode structures such as indium tin oxide structures formed on a thin-film encapsulation layer or polarizer may be used as electrodes for a touch sensor. Displays may have active regions and inactive peripheral portions. The displays may have edge portions that are bent along a bend axis that is within the active region to form a borderless display. Virtual buttons may be formed on the bent edge portions.

摘要翻译： 可以提供诸如有机发光二极管显示器的显示器具有触摸感测能力。 触摸传感器可以由位于薄膜封装层或偏振器的一个或多个侧面上的电极形成。 单面或双面触摸传感器面板可以附接到偏振器的上表面或下表面。 控制电路可以用于使用控制线网格来向显示器中的发光二极管提供控制信号。 控制线和形成在薄膜封装层或偏振片上的铟锡氧化物结构之类的透明电极结构可用作触摸传感器的电极。 显示器可能具有活动区域和不活动的外围部分。 显示器可以具有沿着在有效区域内的弯曲轴线弯曲以形成无边界显示器的边缘部分。 虚拟按钮可以形成在弯曲的边缘部分上。

公开(公告)号：US5552332A

公开(公告)日：1996-09-03

申请号：US460339

申请日：1995-06-02

申请人： Hsing-Huang Tseng ,  Philip J. Tobin ,  Paul G. Y. Tsui ,  Shih W. Sun ,  Stephen S. Poon

发明人： Hsing-Huang Tseng ,  Philip J. Tobin ,  Paul G. Y. Tsui ,  Shih W. Sun ,  Stephen S. Poon

IPC分类号： H01L21/265 ,  H01L21/28 ,  H01L21/336 ,  H01L29/10 ,  H01L21/02

CPC分类号： H01L29/6659 ,  H01L21/26513 ,  H01L21/28176 ,  H01L29/1033 ,  H01L29/6656 ,  H01L29/7842 ,  Y10S438/91

摘要： A process for the fabrication of an MOSFET device includes the formation of a buffer layer (28) overlying the surface of a semiconductor substrate (14) adjacent to a gate electrode (18). A defect compensating species is diffused through the buffer layer (28) and through a gate dielectric layer (12) to form a defect-compensating region (30) at the surface (14) of the semiconductor substrate (10). The defect-compensating region (30) in conjunction with the buffer layer (28) minimize and control the population of point defects in the channel region (22) of the semiconductor substrate (10). By controlling the population of point defects in the channel region (22), a substantially uniform doping profile is maintained in a shallow doped region (16) formed in the semiconductor substrate (10) at the substrate surface (14). The maintenance of a uniform doping profile in the shallow doped region (16) results in improved threshold voltage stability as the lateral dimension of the channel region (22) is reduced.

摘要翻译： 用于制造MOSFET器件的工艺包括形成覆盖在与栅电极（18）相邻的半导体衬底（14）的表面上的缓冲层（28）。 缺陷补偿物质通过缓冲层（28）和栅极电介质层（12）扩散，以在半导体衬底（10）的表面（14）处形成缺陷补偿区域（30）。 与缓冲层（28）结合的缺陷补偿区域（30）最小化并控制半导体衬底（10）的沟道区域（22）中的点缺陷的群体。 通过控制沟道区域（22）中的点缺陷的群体，在衬底表面（14）处形成在半导体衬底（10）中的浅掺杂区域（16）中保持基本均匀的掺杂分布。 在浅掺杂区域（16）中维持均匀的掺杂分布导致当沟道区域（22）的横向尺寸减小时阈值电压稳定性得到改善。

公开(公告)号：US4829024A

公开(公告)日：1989-05-09

申请号：US239919

申请日：1988-09-02

申请人： Jeffrey L. Klein ,  Stephen S. Poon ,  Mark S. Swenson ,  Sudhir K. Madan

发明人： Jeffrey L. Klein ,  Stephen S. Poon ,  Mark S. Swenson ,  Sudhir K. Madan

IPC分类号： H01L21/285 ,  H01L21/3213 ,  H01L21/768

CPC分类号： H01L21/32137 ,  H01L21/28525 ,  H01L21/76879

摘要： A semiconductor process is provided for the formation of a very low resistance contact. After a straight wall contact is formed conventionally above a silicon substrate, a blanket metal barrier layer is deposited. A plurality of planar polysilicon layers are deposited above the metal barrier layer. The polysilicon layers have varying doping levels and are etched away. A byproduct gas of the etch reaction is monitored and the transition between polysilicon layers can be accurately noted. In this way, a layer of doped polysilicon is left above the metal barrier in the contact region. Metal may then be patterned over the entire structure to provide a low resistance reliable contact.

摘要翻译： 提供半导体工艺以形成非常低的电阻接触。 在硅衬底上常规形成直壁接触之后，沉积橡皮布金属阻挡层。 在金属阻挡层上方沉积多个平面多晶硅层。 多晶硅层具有改变的掺杂水平并被蚀刻掉。 监测蚀刻反应的副产物气体，并且可以准确地注意到多晶硅层之间的转变。 以这种方式，在接触区域中的金属阻挡层上方留下掺杂多晶硅层。 然后可以在整个结构上对金属进行图案化以提供低电阻可靠的接触。

公开(公告)号：US09400576B2

公开(公告)日：2016-07-26

申请号：US13186238

申请日：2011-07-19

申请人： Wei Chen ,  Steven P. Hotelling ,  John Z. Zhong ,  Shih-Chang Chang ,  Stephen S. Poon

发明人： Wei Chen ,  Steven P. Hotelling ,  John Z. Zhong ,  Shih-Chang Chang ,  Stephen S. Poon

IPC分类号： G09G3/30 ,  G06F3/044 ,  G06F1/16 ,  G06F3/0488

CPC分类号： G06F3/044 ,  G06F1/1601 ,  G06F1/1643 ,  G06F3/0412 ,  G06F3/0416 ,  G06F3/047 ,  G06F3/04886 ,  G06F2203/04112 ,  H01L27/323 ,  H01L27/3276 ,  H01L27/3288 ,  H01L27/3293 ,  H01L51/5237 ,  H01L51/5246 ,  H01L51/5253 ,  H01L51/5281 ,  H01L51/5284 ,  H01L2251/5338

摘要： Displays such as organic light-emitting diode displays may be provided with touch sensing capabilities. A touch sensor may be formed from electrodes located on a thin-film encapsulation layer or one or more sides of a polarizer. A single-sided or double-sided touch sensor panel may be attached to the upper or lower surface of a polarizer. Control circuitry may be used to provide control signals to light-emitting diodes in the display using a grid of control lines. The control lines and transparent electrode structures such as indium tin oxide structures formed on a thin-film encapsulation layer or polarizer may be used as electrodes for a touch sensor. Displays may have active regions and inactive peripheral portions. The displays may have edge portions that are bent along a bend axis that is within the active region to form a borderless display. Virtual buttons may be formed on the bent edge portions.

摘要翻译： 可以提供诸如有机发光二极管显示器的显示器具有触摸感测能力。 触摸传感器可以由位于薄膜封装层或偏振器的一个或多个侧面上的电极形成。 单面或双面触摸传感器面板可以附接到偏振器的上表面或下表面。 控制电路可以用于使用控制线网格来向显示器中的发光二极管提供控制信号。 控制线和形成在薄膜封装层或偏振片上的铟锡氧化物结构之类的透明电极结构可用作触摸传感器的电极。 显示器可能具有活动区域和不活动的外围部分。 显示器可以具有沿着在有效区域内的弯曲轴线弯曲以形成无边界显示器的边缘部分。 虚拟按钮可以形成在弯曲的边缘部分上。

公开(公告)号：US20120009703A1

公开(公告)日：2012-01-12

申请号：US13234072

申请日：2011-09-15

申请人： Casey J. FEINSTEIN ,  John Z. Zhong ,  Lynn R. Youngs ,  Stephen S. Poon

发明人： Casey J. FEINSTEIN ,  John Z. Zhong ,  Lynn R. Youngs ,  Stephen S. Poon

IPC分类号： H01L33/08

CPC分类号： G06F3/0416 ,  G02F1/1333 ,  G02F1/1368 ,  G06F3/044 ,  H01L27/1266 ,  Y10T29/49155

摘要： A method of fabricating a display panel from a thin substrate using a carrier substrate is disclosed. The method includes depositing a bonding agent on a first surface of the thin substrate; depositing a bonding agent on a second surface of the carrier substrate; bonding the thin substrate and the carrier substrate with the bonding agent deposited on the first surface and the second surface; performing thin film processing on a third surface of the thin substrate opposite the first surface; and separating the processed thin substrate from the carrier substrate. The thin substrate has a thickness less than a required thickness for sustaining thin film processing while a thickness of the bonded thin substrate and the carrier substrates is greater than or equal to that the required thickness.

摘要翻译： 公开了一种使用载体衬底从薄衬底制造显示面板的方法。 该方法包括在薄衬底的第一表面上沉积粘合剂; 在所述载体基板的第二表面上沉积粘合剂; 用沉积在第一表面和第二表面上的粘结剂粘合薄基片和载体基片; 在与第一表面相对的薄基板的第三表面上执行薄膜处理; 并且将经处理的薄衬底与载体衬底分离。 薄基板的厚度小于用于维持薄膜处理所需的厚度，而粘合的薄基板和载体基板的厚度大于或等于所需的厚度。

公开(公告)号：US5436488A

公开(公告)日：1995-07-25

申请号：US332236

申请日：1994-10-31

申请人： Stephen S. Poon ,  Hsing-Huang Tseng

发明人： Stephen S. Poon ,  Hsing-Huang Tseng

IPC分类号： H01L21/76 ,  H01L21/762 ,  H01L21/763 ,  H01L27/12

CPC分类号： H01L21/76224 ,  H01L21/763 ,  Y10S148/05

摘要： The reliability of integrated circuits fabricated with trench isolation is improved by increasing the thickness of the gate dielectric overlying the trench corner. After the trench isolation region (40, 56) has been formed a thin layer of silicon dioxide (44) is chemically vapor deposited over the trench isolation region (44) and the adjacent active region (23). A transistor gate electrode (46) is subsequently formed over the thin layer of silicon dioxide (44). The thin layer of silicon dioxide (44) increases the thickness of the gate dielectric that lies between the transistor gate electrode (46) and the trench corner, and therefore the breakdown voltage of the gate dielectric at the trench corner is increased.

摘要翻译： 通过增加覆盖在沟槽角上的栅极电介质的厚度来提高通过沟槽隔离制造的集成电路的可靠性。 在已经形成沟槽隔离区域（40,56）之后，在沟槽隔离区域（44）和相邻的有源区域（23）上化学气相沉积薄层二氧化硅（44）。 随后在二氧化硅（44）的薄层上形成晶体管栅电极（46）。 二氧化硅（44）的薄层增加位于晶体管栅极（46）和沟槽角之间的栅极电介质的厚度，因此沟槽角处的栅极电介质的击穿电压增加。

公开(公告)号：US09063605B2

公开(公告)日：2015-06-23

申请号：US13234072

申请日：2011-09-15

申请人： Casey J. Feinstein ,  John Z. Zhong ,  Lynn R. Youngs ,  Stephen S. Poon

发明人： Casey J. Feinstein ,  John Z. Zhong ,  Lynn R. Youngs ,  Stephen S. Poon

IPC分类号： H05K3/02 ,  H05K3/10 ,  G06F3/041 ,  G02F1/1333 ,  G06F3/044 ,  H01L27/12 ,  G02F1/1368

CPC分类号： G06F3/0416 ,  G02F1/1333 ,  G02F1/1368 ,  G06F3/044 ,  H01L27/1266 ,  Y10T29/49155

摘要： A method of fabricating a display panel from a thin substrate using a carrier substrate is disclosed. The method includes depositing a bonding agent on a first surface of the thin substrate; depositing a bonding agent on a second surface of the carrier substrate; bonding the thin substrate and the carrier substrate with the bonding agent deposited on the first surface and the second surface; performing thin film processing on a third surface of the thin substrate opposite the first surface; and separating the processed thin substrate from the carrier substrate. The thin substrate has a thickness less than a required thickness for sustaining thin film processing while a thickness of the bonded thin substrate and the carrier substrates is greater than or equal to that the required thickness.

摘要翻译： 公开了一种使用载体衬底从薄衬底制造显示面板的方法。 该方法包括在薄衬底的第一表面上沉积粘合剂; 在所述载体基板的第二表面上沉积粘合剂; 用沉积在第一表面和第二表面上的粘结剂粘合薄基片和载体基片; 在与第一表面相对的薄基板的第三表面上执行薄膜处理; 并且将经处理的薄衬底与载体衬底分离。 薄基板的厚度小于用于维持薄膜处理所需的厚度，而粘合的薄基板和载体基板的厚度大于或等于所需的厚度。