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公开(公告)号：US07235859B2
公开(公告)日：2007-06-26
申请号：US10957492
申请日：2004-10-01
IPC分类号： H01L29/00
CPC分类号： H01L23/5254 , H01L23/5258 , H01L2924/0002 , H01L2924/00
摘要： An arrangement for protecting fuses/anti-fuses on chips which serve to activate redundant circuits or chip functions includes a passivation layer (e.g., hard passivation) arranged on a fully processed chip with the exception of metal contacts of a metallization level and the fuses. The chip is provided with a redistribution layer that is electrically contact-connected to the metallization level, and to a process for protecting such fuses/anti-fuses. The invention is now based on the object of ensuring sufficient protection of fuses/anti-fuses on integrated circuits. This is achieved by virtue of the fact that a dielectric (3.1, 3.2), which covers at least the region of the fuses/anti-fuses (4) and to which the redistribution layer (2) comprising the combination of materials Cu/Ni/Au is applied, is arranged on the passivation layer (5).
摘要翻译： 用于保护用于激活冗余电路或芯片功能的芯片上的熔断器/防熔丝的布置包括布置在完全处理的芯片上的钝化层（例如，硬钝化），除了金属化水平的金属触点和熔丝之外。 该芯片设置有与金属化层电接触连接的再分布层，以及用于保护这种保险丝/防熔丝的工艺。 本发明的目的在于确保集成电路上的保险丝/抗熔断器的充分保护。 这通过以下事实来实现：电介质（3.1,3.2），其至少覆盖保险丝/抗熔丝（4）的区域，再分布层（2）包括材料Cu / Ni的组合 / Au被布置在钝化层（5）上。
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公开(公告)号：US20050258506A1
公开(公告)日：2005-11-24
申请号：US10957492
申请日：2004-10-01
IPC分类号： H01L21/82 , H01L23/28 , H01L23/525 , H01L29/00
CPC分类号： H01L23/5254 , H01L23/5258 , H01L2924/0002 , H01L2924/00
摘要： An arrangement for protecting fuses/anti-fuses on chips which serve to activate redundant circuits or chip functions includes a passivation layer (e.g., hard passivation) arranged on a fully processed chip with the exception of metal contacts of a metallization level and the fuses. The chip is provided with a redistribution layer that is electrically contact-connected to the metallization level, and to a process for protecting such fuses/anti-fuses. The invention is now based on the object of ensuring sufficient protection of fuses/anti-fuses on integrated circuits. This is achieved by virtue of the fact that a dielectric (3.1, 3.2), which covers at least the region of the fuses/anti-fuses (4) and to which the redistribution layer (2) comprising the combination of materials Cu/Ni/Au is applied, is arranged on the passivation layer (5).
摘要翻译： 用于保护用于激活冗余电路或芯片功能的芯片上的熔断器/防熔丝的布置包括布置在完全处理的芯片上的钝化层（例如，硬钝化），除了金属化水平的金属触点和熔丝之外。 该芯片设置有与金属化层电接触连接的再分布层，以及用于保护这种保险丝/防熔丝的工艺。 本发明的目的在于确保集成电路上的保险丝/抗熔断器的充分保护。 这通过以下事实来实现：电介质（3.1,3.2），其至少覆盖保险丝/抗熔丝（4）的区域，再分布层（2）包括材料Cu / Ni的组合 / Au被布置在钝化层（5）上。
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公开(公告)号：US07393782B2
公开(公告)日：2008-07-01
申请号：US11051548
申请日：2005-02-04
IPC分类号： H01L21/44
CPC分类号： H01L21/76885 , H01L21/76834
摘要： Structures for signal distribution are produced by applying a metallic seed layer over a semiconductor body. An insulating layer is applied over the metallic seed layer and openings in the insulating layer are produced by photolithographic patterning of the insulating layer. Each opening in the insulating layer is trapezoidal in cross section such that an upper portion of the insulating layer is wider than a lower portion of the insulating layer. A conductor is selectively formed over exposed portions of the metallic seed layer. After selectively forming the conductor, the insulating layer is anisotropically etched such that portions of the insulating layer abutting sidewalls of the conductor remain. Alternatively, a second insulating layer can be formed and anisotropically etched.
摘要翻译： 用于信号分配的结构通过在半导体本体上施加金属种子层而产生。 在金属种子层上施加绝缘层，并通过绝缘层的光刻图案来制造绝缘层中的开口。 绝缘层中的每个开口的横截面为梯形，使得绝缘层的上部比绝缘层的下部更宽。 在金属种子层的暴露部分上选择性地形成导体。 在选择性地形成导体之后，绝缘层被各向异性地蚀刻，使得绝缘层邻接导体的侧壁的部分保留。 或者，可以形成第二绝缘层并各向异性蚀刻。
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公开(公告)号：US20050191837A1
公开(公告)日：2005-09-01
申请号：US11051548
申请日：2005-02-04
IPC分类号： H01L21/44 , H01L21/4763 , H01L21/768
CPC分类号： H01L21/76885 , H01L21/76834
摘要： Structures for signal distribution are produced by applying a metallic seed layer over a semiconductor body. An insulating layer is applied over the metallic seed layer and openings in the insulating layer are produced by photolithographic patterning of the insulating layer. Each opening in the insulating layer is trapezoidal in cross section such that an upper portion of the insulating layer is wider than a lower portion of the insulating layer. A conductor is selectively formed over exposed portions of the metallic seed layer. After selectively forming the conductor, the insulating layer is anisotropically etched such that portions of the insulating layer abutting sidewalls of the conductor remain. Alternatively, a second insulating layer can be formed and anisotropically etched.
摘要翻译： 用于信号分配的结构通过在半导体本体上施加金属种子层而产生。 在金属种子层上施加绝缘层，并通过绝缘层的光刻图案来制造绝缘层中的开口。 绝缘层中的每个开口的横截面为梯形，使得绝缘层的上部比绝缘层的下部更宽。 在金属种子层的暴露部分上选择性地形成导体。 在选择性地形成导体之后，绝缘层被各向异性地蚀刻，使得绝缘层邻接导体的侧壁的部分保留。 或者，可以形成第二绝缘层并各向异性蚀刻。
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公开(公告)号：US20050186786A1
公开(公告)日：2005-08-25
申请号：US11046663
申请日：2005-01-28
IPC分类号： H01L21/768 , H01L23/532 , H05K3/10 , H05K3/24 , H01L21/4763 , H01L21/44
CPC分类号： H01L21/76843 , H01L21/76852 , H01L21/76873 , H01L23/53238 , H01L2221/1078 , H01L2924/0002 , H05K3/108 , H05K3/243 , H05K2203/0505 , H01L2924/00
摘要： The invention, which relates to a method for fabricating metallic interconnects with copper-nickel-gold layer construction on electronic components, is based on the object of specifying a method by means of which it is possible to fabricate such metallic interconnects on different electronic components cost-effectively by means of the known and tried and tested methods which have a comprehensive corrosion protection. According to the invention, the object is achieved by virtue of the fact that the interconnects are embodied such that they are completely encapsulated by being deposited in a manner buried in a patterned dielectric layer in the lower region and being covered in the upper region by a nickel-gold layer adjoining the lower encapsulation without any gaps.
摘要翻译： 本发明涉及一种在电子部件上用铜 - 镍 - 金层构造制造金属互连的方法，其目的是确定一种方法，通过该方法可以在不同的电子部件成本上制造这种金属互连 - 通过已知和经过测试的方法有效地进行了全面的防腐蚀保护。 根据本发明，目的是通过这样一个事实来实现的：互连被实现为使得它们被完全地被封装在一个掩埋在下部区域中的图案化电介质层中并被上部区域覆盖的方式 镍金层与下封装相邻，无任何间隙。
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公开(公告)号：US07172966B2
公开(公告)日：2007-02-06
申请号：US11046663
申请日：2005-01-28
IPC分类号： H01L21/44
CPC分类号： H01L21/76843 , H01L21/76852 , H01L21/76873 , H01L23/53238 , H01L2221/1078 , H01L2924/0002 , H05K3/108 , H05K3/243 , H05K2203/0505 , H01L2924/00
摘要： The invention, which relates to a method for fabricating metallic interconnects with copper-nickel-gold layer construction on electronic components, is based on the object of specifying a method by means of which it is possible to fabricate such metallic interconnects on different electronic components cost-effectively by means of the known and tried and tested methods which have a comprehensive corrosion protection. According to the invention, the object is achieved by virtue of the fact that the interconnects are embodied such that they are completely encapsulated by being deposited in a manner buried in a patterned dielectric layer in the lower region and being covered in the upper region by a nickel-gold layer adjoining the lower encapsulation without any gaps.
摘要翻译： 本发明涉及一种在电子部件上用铜 - 镍 - 金层构造制造金属互连的方法，其目的是确定一种方法，通过该方法可以在不同的电子部件成本上制造这种金属互连 - 通过已知和经过测试的方法有效地进行了全面的防腐蚀保护。 根据本发明，目的是通过这样一个事实来实现的：互连被实现为使得它们被完全地被封装在一个掩埋在下部区域中的图案化电介质层中并被上部区域覆盖的方式 镍金层与下封装相邻，无任何间隙。
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7.发明授权Connection between a semiconductor chip and an external conductor structure and method for producing it 有权半导体芯片和外部导体结构之间的连接及其制造方法公开(公告)号：US07169647B2
公开(公告)日：2007-01-30
申请号：US10842259
申请日：2004-05-07
CPC分类号： H01L24/10 , H01L24/13 , H01L2224/0236 , H01L2224/05001 , H01L2224/05008 , H01L2224/05016 , H01L2224/05024 , H01L2224/05026 , H01L2224/05568 , H01L2224/05569 , H01L2224/13 , H01L2224/13099 , H01L2924/01005 , H01L2924/01029 , H01L2924/01033 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/00 , H01L2224/05644 , H01L2924/00014 , H01L2224/05144 , H01L2224/05147 , H01L2224/05155
摘要： A conductive connection is made between a semiconductor chip and an external conductor structure. An elevation element is applied on the surface of the semiconductor chip and a soldering island is arranged on the elevation element. An interconnect is produced below the soldering island as far as a bonding island or an I/O pad. Increased reliability of conductive connections of the bonding island or the I/O pad to an external conductive structure can be achieved by preventing the flowing-away of the solder and the oxidation or corrosion of the conductive layer.
摘要翻译： 在半导体芯片和外部导体结构之间形成导电连接。 在半导体芯片的表面上施加高度元件，在升降元件上设置焊接岛。 在焊岛下方产生互连，只要接合岛或I / O焊盘即可。 可以通过防止焊料的流失和导电层的氧化或腐蚀来实现将接合岛或I / O焊盘与外部导电结构的导电连接的可靠性提高。
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公开(公告)号：US20050275085A1
公开(公告)日：2005-12-15
申请号：US11140578
申请日：2005-05-27
申请人： Axel Brintzinger , Octavio Trovarelli , Ingo Uhlendorf , Stefan Ruckmich , David Wallis , Fritz Uhlendorf , Helga Uhlendorf
发明人： Axel Brintzinger , Octavio Trovarelli , Ingo Uhlendorf , Stefan Ruckmich , David Wallis , Fritz Uhlendorf , Helga Uhlendorf
IPC分类号： H01L23/12 , H01L23/522 , H01L23/528
CPC分类号： H01L23/5222 , H01L23/5225 , H01L2924/0002 , H01L2924/00
摘要： An arrangement reduces the electrical crosstalk on a chip, in particular between adjacent conductors of the redistribution routing and/or between the redistribution routing on the first passivation on the chip and the metallization of the chip. In one aspect, the arrangement reduces the crosstalk between the redistribution wiring on a chip and its metallization and can be realized simply and independently at the front end. This is achieved by at least an additional conductor (10) being respectively arranged between adjacent conductors of the redistribution routing (1) and/or at least a second passivation (7) with a lower dielectric constant of a preferred “cold dielectric” being arranged between the redistribution routing (1) and the first passivation (2) on the active region of the chip (3).
摘要翻译： 一种布置减少了芯片上的电串扰，特别是在再分配路由的相邻导体之间和/或芯片上的第一钝化上的再分配布线之间以及芯片的金属化之间的电串扰。 在一个方面，该布置减少了芯片上的再分配布线与其金属化之间的串扰，并且可以在前端简单且独立地实现。 这通过分别布置在再分配路由（1）的相邻导体和/或至少第二钝化层（7）之间的至少一个额外的导体（10）来实现，其中优选的“冷电介质”的较低介电常数被布置 在芯片（3）的有源区域上的再分配路由（1）和第一钝化（2）之间。
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公开(公告)号：US20060121257A1
公开(公告)日：2006-06-08
申请号：US11251594
申请日：2005-10-14
CPC分类号： H01L23/49827 , H01L21/4846 , H01L21/486 , H01L2924/0002 , H05K1/0287 , H05K1/0306 , H05K2201/09609 , Y10S438/976 , Y10T428/24273 , Y10T428/24322 , Y10T428/24331 , Y10T428/24917 , H01L2924/00
摘要： The invention relates to a method for producing a rewiring printed circuit board with a substrate wafer having passage connections between a first and a second surface. One embodiment of the method comprises applying and patterning masking layers on the first and the second surfaces, thereby uncovering a first contact location on the first surface and a second contact location on the second surface; applying a protective layer to the second surface in order to protect the corresponding masking layer and the second contact location during subsequent method steps; applying a first conductor structure to the first surface, the first conductor structure on the first surface covering the first contact location; removing the protective layer on the second surface; and applying a second conductor structure to the second surface, the second conductor structure on the second surface covering the second contact location.
摘要翻译： 本发明涉及一种用于生产具有在第一和第二表面之间具有通道连接的基底晶片的再布线印刷电路板的方法。 该方法的一个实施例包括在第一和第二表面上施加和图案化掩模层，从而揭露第一表面上的第一接触位置和第二表面上的第二接触位置; 在第二表面施加保护层，以便在随后的方法步骤期间保护相应的掩蔽层和第二接触位置; 将第一导体结构施加到第一表面，第一表面上的第一导体结构覆盖第一接触位置; 去除第二表面上的保护层; 以及将第二导体结构施加到所述第二表面，所述第二表面上的所述第二导体结构覆盖所述第二接触位置。
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10.发明申请Electronic component with compliant elevations having electrical contact areas and method for producing it 有权具有具有电接触区域的顺应性高度的电子部件及其制造方法公开(公告)号：US20050127521A1
公开(公告)日：2005-06-16
申请号：US10997761
申请日：2004-11-24
IPC分类号： H01L21/4763 , H01L21/60 , H01L23/48 , H01L23/498 , H01L23/50 , H01L23/52 , H01L29/40
CPC分类号： H01L23/49811 , H01L2924/0002 , H01L2924/12044 , H01L2924/00
摘要： An electronic component includes compliant elevations having electrical contact areas for contact-connecting the component to an electronic circuit. The compliant elevations are arranged on a surface of the component and the electrical contact areas are arranged on the tip of the compliant elevations. The electrical contact with the electronic circuit is embodied by means of electrical conductive tracks arranged on the surface of the component. The conductive tracks ascend on the outer surfaces of the compliant elevations to the electrical contact areas.
摘要翻译： 电子部件包括具有用于将部件与电子电路接触连接的电接触区域的柔性凸起。 顺应性高度布置在部件的表面上，并且电接触区域布置在顺应性高度的尖端上。 与电子电路的电接触通过布置在部件的表面上的导电轨道来实现。 导电轨道在顺应性高度的外表面上升到电接触区域。
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