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公开(公告)号：US20180090378A1
公开(公告)日：2018-03-29
申请号：US15522861
申请日：2016-09-29
发明人： Yanchun LU , Xuebing JIANG
IPC分类号： H01L21/77 , H01L21/12 , H01L23/552 , G02F1/1368
CPC分类号： H01L21/77 , G02F1/13454 , G02F1/1368 , G02F2001/136236 , G09G2300/0408 , H01L21/12 , H01L23/552 , H01L27/12
摘要： An array substrate and a method for manufacturing the same, and a display device are provided. The method includes: forming a thin film transistor (TFT) structure of a display region and a TFT structure of the GOA region on a substrate; sequentially forming a first insulating layer, an indium tin oxide (ITO) layer and a photoresist layer on the TFT structure; exposing and developing the photoresist layer using a halftone mask plate, and etching the ITO layer, to form an electrode layer in the GOA region and an electrode layer in the display region; and ashing the remaining photoresist to completely remove the photoresist on the electrode layer in the display region and to thinning the photoresist on the electrode layer in the GOA region.
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公开(公告)号：US20210035516A1
公开(公告)日：2021-02-04
申请号：US16825842
申请日：2020-03-20
发明人： Chengying CAO , Xingyi LIU , Xuebing JIANG , Guangying MOU , Peng WU
IPC分类号： G09G3/36
摘要： A shift register includes an output sub-circuit and a compensation sub-circuit. The output sub-circuit is coupled to a pull-up node, a clock signal terminal and a signal output terminal. The compensation sub-circuit is coupled to the pull-up node, the clock signal terminal and the signal output terminal. The output sub-circuit is configured to transmit a voltage of the clock signal terminal to the signal output terminal under control of a voltage of the pull-up node, The compensation sub-circuit is configured to transmit a voltage of the signal output terminal to the pull-up node under control of the voltage of the pull-up node and the voltage of the clock signal terminal.
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3.发明申请公开(公告)号：US20200219901A1
公开(公告)日：2020-07-09
申请号：US16827151
申请日：2020-03-23
发明人： Jilei GAO , Xuebing JIANG , Songmei SUN , Peng WU , Jian ZHAO , Yang ZHANG , Mo CHEN
IPC分类号： H01L27/12 , H01L29/786 , H01L27/02 , H01L29/66
摘要： A thin film transistor, a manufacturing method thereof, an array substrate and a display panel are provided. The thin film transistor includes: a base substrate; and a gate electrode, a gate insulating layer, an active layer and a source/drain electrode layer which are on the base substrate. The source/drain electrode layer includes a source electrode and a drain electrode. The thin film transistor further includes a light blocking layer surrounding the active layer.
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公开(公告)号：US20180267375A1
公开(公告)日：2018-09-20
申请号：US15541566
申请日：2016-08-09
发明人： Xuebing JIANG , Jilei GAO
IPC分类号： G02F1/1362 , H01L27/12 , G02F1/1343 , G02F1/1333 , G02F1/1339 , G02F1/1335
CPC分类号： G02F1/136259 , G02F1/133345 , G02F1/133514 , G02F1/1339 , G02F1/13392 , G02F1/134309 , G02F1/13452 , G02F1/136204 , G02F1/136286 , G02F2001/134318 , G02F2001/136263 , G02F2001/136295 , G02F2202/16 , H01L27/124 , H01L27/1262
摘要： The present application discloses a display panel including an array substrate and an opposing substrate facing the array substrate; a data line layer having a plurality of data lines on the array substrate; a passivation layer on a side of the data line layer proximal to the opposing substrate; a sealant layer on a side of the passivation layer distal to the data line layer, sealing the array substrate and the opposing substrate together; the display panel having a first area enclosed by the sealant layer and a second area outside of the first area and the sealant layer; the plurality of data lines extending from the first area into the second area; and a common electrode layer on a side of the sealant layer distal to the passivation layer. The common electrode layer includes a portion having a plurality of connections, and a plurality of slits spaced apart from each other by the plurality of connections, the plurality of slits and the plurality of connections extending from the first area into the second area, each of the plurality of connections is between two adjacent slits; each of the plurality of connections has a first portion in the first area and a second portion in the second area.
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5.发明申请公开(公告)号：US20170299907A1
公开(公告)日：2017-10-19
申请号：US15324295
申请日：2016-06-07
发明人： Jian ZHAO , Xuebing JIANG , Jinliang LIU
IPC分类号： G02F1/1368 , G02F1/1343 , H01L27/12 , G09G3/36 , G02F1/1362 , H03K17/687
CPC分类号： G02F1/1368 , G02F1/134309 , G02F1/136286 , G02F2001/134345 , G02F2001/136295 , G02F2201/121 , G02F2201/123 , G09G3/3648 , G09G3/3655 , G09G3/3666 , G09G2300/0426 , G09G2300/0814 , G09G2320/0209 , G09G2320/0223 , G09G2320/0242 , G09G2320/0247 , G09G2320/0257 , H01L27/124 , H01L27/1259 , H03K17/6871
摘要： The present disclosure provides an array substrate. The array substrate includes a display region and a plurality of control lines, the display region being divided into a plurality of sub-regions, each sub-region comprising a plurality of pixels, each pixel including a common electrode. Common electrodes in pixels in a sub-region are electrically connected together; common electrodes in two sub-regions are connected by a switching unit; and a control line is connected with the common electrodes in the sub-region to provide a common voltage signal to the common electrodes.
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公开(公告)号：US20200219456A1
公开(公告)日：2020-07-09
申请号：US15753340
申请日：2017-07-13
发明人： Jilei GAO , Jinliang LIU , Yang ZHANG , Xuebing JIANG , Songmei SUN
IPC分类号： G09G3/36 , G02F1/1343 , G02F1/1362 , G09G3/20
摘要： An array substrate, a display panel, a display device and a method for designing the display panel are provided. The array substrate includes a plurality of pixel units, wherein each of the pixel units includes a plurality of sub-pixels, each of the sub-pixels includes a pixel electrode, and the pixel electrode includes a plurality of strip-shaped sub-pixel electrodes arranged in a comb-teeth form, and the sub-pixels of one of the pixel units include at least two sub-pixels. A width of the strip-shaped sub-pixel electrode of any one of the at least two sub-pixels is different from a width of the strip-shaped sub-pixel electrode of any other one of the at least two sub-pixels, and/or an interval between the strip-shaped sub-pixel electrodes of any one of the at least two sub-pixels is different from an interval between the strip-shaped sub-pixel electrodes of any other one of the at least two sub-pixels.
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公开(公告)号：US20180052368A1
公开(公告)日：2018-02-22
申请号：US15537184
申请日：2016-10-21
发明人： Xuebing JIANG
IPC分类号： G02F1/1337 , G02F1/1362 , G02F1/1343
CPC分类号： G02F1/133753 , G02F1/133707 , G02F1/133784 , G02F1/133788 , G02F1/134309 , G02F1/13439 , G02F1/136286 , G02F1/1368 , G02F2001/133757 , G02F2001/133761 , G02F2001/133776 , G02F2001/134372 , G02F2001/136295 , G02F2201/123 , G02F2203/01
摘要： A display substrate and a manufacturing method thereof and a display device are disclosed. The display substrate includes a plurality of pixel regions, an alignment film for providing a pre-tilt angle for liquid crystal molecules being disposed in the plurality of pixel regions. In each of the pixel regions, a surface of the alignment film has a plurality of orientation grooves extending along at least two directions. The alignment film is made of a transparent material, and therefore, an aperture ratio of pixels will not be affected, and an influence on other structures of the display substrate either will not be generated.
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公开(公告)号：US20180051981A1
公开(公告)日：2018-02-22
申请号：US15658630
申请日：2017-07-25
发明人： Xuebing JIANG
IPC分类号： G01B11/16
CPC分类号： G01B11/161 , G01B11/306 , G02F1/1309
摘要： A measuring device and method for a substrate warping amount includes a first substrate and a second substrate disposed oppositely. The measuring device includes a light source, a measuring eyepiece and a processor. The light source is configured to emit a monochromatic light to a region to be measured of the display motherboard, and form a Newton ring interference pattern. The measuring eyepiece is configured to acquire the Newton ring interference pattern and measure a diameter and a corresponding order number of each interference fringe in the Newton ring interference pattern. The processor is connected to the measuring eyepiece and configured to obtain a thickness of an air layer at each interference fringe according to the diameter and the corresponding order number of each interference fringe and a wavelength of the monochromatic light, to obtain a warping amount of the region to be measured of the display motherboard.
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公开(公告)号：US20160027801A1
公开(公告)日：2016-01-28
申请号：US14435913
申请日：2014-08-15
发明人： Xuebing JIANG , Lin LIN
CPC分类号： H01L27/124 , G02F1/13624 , H01L21/77 , H01L27/12 , H01L27/1222 , H01L27/1225 , H01L27/1248 , H01L27/1288 , H01L29/04 , H01L29/16 , H01L29/22 , H01L29/24 , H01L29/66765 , H01L29/66969 , H01L29/786 , H01L29/78678 , H01L29/7869
摘要： An array substrate, a manufacturing method thereof and a display panel are disclosed. The array substrate comprises: a base substrate (200) and gate lines (202), data lines (205) and a plurality of pixel units (20). Each pixel unit (20) includes a first thin-film transistor (TFT), a pixel electrode (208) and at least second TFT connected in series with the first TFT. The pixel electrode (208) is connected with a drain electrode (207′) of the second TFT; a source electrode (206′) of the second TFT is connected with a drain electrode (207) of the first TFT; and a source electrode (206) of the first TFT is connected with the data line (205). The array substrate can reduce the leakage current when the TFTs are switched off.
摘要翻译： 公开了阵列基板，其制造方法和显示面板。 阵列基板包括：基底基板（200）和栅极线（202），数据线（205）和多个像素单元（20）。 每个像素单元（20）包括与第一TFT串联连接的第一薄膜晶体管（TFT），像素电极（208）和至少第二TFT。 像素电极（208）与第二TFT的漏电极（207'）连接; 第二TFT的源电极（206'）与第一TFT的漏电极（207）连接; 并且第一TFT的源电极（206）与数据线（205）连接。 当TFT关闭时，阵列基板可以减小漏电流。
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10.发明申请公开(公告)号：US20190056614A1
公开(公告)日：2019-02-21
申请号：US15764303
申请日：2017-08-10
发明人： Yujuan ZHAN , Xuebing JIANG , Peng WU , Jilei GAO
IPC分类号： G02F1/1339 , G02F1/1335 , G02F1/1368
摘要： The embodiments of the disclosure relate to the field of display technology and provide a counter substrate, a liquid crystal display panel and a method for eliminating bright spots, which can avoid bright spots caused by foreign bodies and reduce cost. The counter substrate includes a substrate, a black matrix and an orientation layer disposed on the substrate, and a wall. The black matrix at least includes a plurality of first light shielding strips. An orthographic projection of the wall on the substrate is covered by an orthographic projection of the plurality of first light shielding strips on the substrate. The wall extends along a first direction that intersects an orientation direction of the orientation layer.
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