公开(公告)号：US20060146593A1

公开(公告)日：2006-07-06

申请号：US11293880

申请日：2005-12-02

申请人： Bernd Klehn ,  Hermann Fischer ,  Eckhard Brass ,  Ralf Klein ,  Thomas Schumann

发明人： Bernd Klehn ,  Hermann Fischer ,  Eckhard Brass ,  Ralf Klein ,  Thomas Schumann

IPC分类号： G11C11/24

CPC分类号： G11C7/1069 ,  G11C7/065 ,  G11C11/4091 ,  G11C11/4096 ,  G11C2207/002 ,  G11C2207/005

摘要： A method for reading data from a dynamic memory circuit is provided, wherein at least one memory cell can be addressed via a word line and a bit line, wherein the memory cell is connected to a first reading amplifier via the bit line, and wherein a switching element, which in the off state isolates the first reading amplifier from the bit line, is provided. The method comprises: a) turning on the switching element to connect the first reading amplifier to the bit line, b) activating the word line to activate the memory cell for reading, c) activating the first reading amplifier to initiate assessment of the information on the bit line, d) turning off the switching element to isolate the first reading amplifier from the bit line, and e) transferring the information which has been read to a data bus.

摘要翻译： 提供了一种用于从动态存储器电路读取数据的方法，其中至少一个存储单元可以经由字线和位线寻址，其中存储单元经由位线连接到第一读取放大器，并且其中 提供了在关断状态下将第一读取放大器与位线隔离的开关元件。 该方法包括：a）打开开关元件以将第一读取放大器连接到位线，b）激活字线以激活用于读取的存储器单元，c）激活第一读取放大器以开始对信息进行评估 位线，d）关断开关元件以将第一读取放大器与位线隔离，以及e）将已经读取的信息传送到数据总线。

公开(公告)号：US07307869B2

公开(公告)日：2007-12-11

申请号：US11293880

申请日：2005-12-02

申请人： Bernd Klehn ,  Hermann Fischer ,  Eckhard Brass ,  Ralf Klein ,  Thomas Schumann

发明人： Bernd Klehn ,  Hermann Fischer ,  Eckhard Brass ,  Ralf Klein ,  Thomas Schumann

IPC分类号： G11C11/24

CPC分类号： G11C7/1069 ,  G11C7/065 ,  G11C11/4091 ,  G11C11/4096 ,  G11C2207/002 ,  G11C2207/005

摘要： A method for reading data from a dynamic memory circuit is provided, wherein at least one memory cell can be addressed via a word line and a bit line, wherein the memory cell is connected to a first reading amplifier via the bit line, and wherein a switching element, which in the off state isolates the first reading amplifier from the bit line, is provided. The method comprises: a) turning on the switching element to connect the first reading amplifier to the bit line, b) activating the word line to activate the memory cell for reading, c) activating the first reading amplifier to initiate assessment of the information on the bit line, d) turning off the switching element to isolate the first reading amplifier from the bit line, and e) transferring the information which has been read to a data bus.

摘要翻译： 提供了一种用于从动态存储器电路读取数据的方法，其中至少一个存储单元可以经由字线和位线寻址，其中存储单元经由位线连接到第一读取放大器，并且其中 提供了在关断状态下将第一读取放大器与位线隔离的开关元件。 该方法包括：a）打开开关元件以将第一读取放大器连接到位线，b）激活字线以激活用于读取的存储器单元，c）激活第一读取放大器以开始对信息进行评估 位线，d）关断开关元件以将第一读取放大器与位线隔离，以及e）将已经读取的信息传送到数据总线。

公开(公告)号：US06838917B2

公开(公告)日：2005-01-04

申请号：US10266354

申请日：2002-10-07

申请人： Eckhard Brass ,  Bernd Klehn ,  Ralf Klein ,  Thoai-Thai Le

发明人： Eckhard Brass ,  Bernd Klehn ,  Ralf Klein ,  Thoai-Thai Le

IPC分类号： G11C7/10 ,  G11C7/22 ,  H03L7/06

CPC分类号： G11C7/1066 ,  G11C7/04 ,  G11C7/1072 ,  G11C7/22 ,  G11C7/222

摘要： A circuit configuration for processing data, particularly a semiconductor memory chip, has a control circuit for setting a phase or frequency relationship between two signals. A digital counter detects a phase or frequency difference between the two signals, and the counter reading is used for regulating the phase or frequency relationship. Trials have shown that the counter reading indicates an operating state in the circuit configuration and therefore represents a simple signal for assessing the operating state of the circuit configuration. Preferably, the counter reading is taken as a basis for adjusting the speed or power of time-critical or performance-critical circuit parts in the circuit configuration so that an operating state with an intermediate switching speed is obtained.

摘要翻译： 用于处理数据的电路配置，特别是半导体存储器芯片，具有用于设置两个信号之间的相位或频率关系的控制电路。 数字计数器检测两个信号之间的相位或频率差，并且计数器读数用于调节相位或频率关系。 试验表明，计数器读数表示电路配置中的工作状态，因此表示用于评估电路配置工作状态的简单信号。 优选地，计数器读数作为调整电路配置中时间关键或性能关键电路部件的速度或功率的基础，从而获得具有中间切换速度的操作状态。

公开(公告)号：US06737895B2

公开(公告)日：2004-05-18

申请号：US10196566

申请日：2002-07-16

申请人： Joachim Schnabel ,  Bernd Klehn ,  Andrea Zuckerstätter ,  Ralf Klein

发明人： Joachim Schnabel ,  Bernd Klehn ,  Andrea Zuckerstätter ,  Ralf Klein

IPC分类号： H03K1722

CPC分类号： G11C7/109 ,  G11C7/1078

摘要： A method for driving a plurality of circuit units to be controlled includes applying a control signal to a control signal connection unit and an activation signal to an activation connection unit. A hold signal is the generated on the in response to the activation signal. This hold signal is combined with the control signal to obtain a modified control signal, which is then made available at an output.

摘要翻译： 用于驱动要控制的多个电路单元的方法包括将控制信号施加到控制信号连接单元和激活信号到激活连接单元。 保持信号是响应于激活信号产生的。 该保持信号与控制信号组合以获得经修改的控制信号，然后在输出端使其可用。

公开(公告)号：US06850099B2

公开(公告)日：2005-02-01

申请号：US10261200

申请日：2002-09-30

申请人： Bernd Klehn ,  Ralf Klein ,  Joachim Schnabel

发明人： Bernd Klehn ,  Ralf Klein ,  Joachim Schnabel

IPC分类号： H03K19/003 ,  H03K19/0185 ,  H03B1/00

CPC分类号： H03K19/018585 ,  H03K19/00346

摘要： In a scalable driver device having a plurality of driver stages whose outputs are connected to a common terminal contact for providing a common output signal, drive parameters of the driver stages, individually or in groups, are so dimensioned that the difference of the edge rise times and/or fall times of the output signal from one active driver stage to the next driver stage to be activated is substantially equal to the difference of the edge rise times and/or fall times from a next activated driver stage to the one activated after that.

摘要翻译： 在具有多个驱动级的可扩展驱动器装置中，其输出连接到用于提供公共输出信号的公共端子触点，驱动器级的驱动参数被单独地或分组地设定为使得边沿上升时间的差 和/或从一个有效驱动级到待激活的下一个驱动器级的输出信号的下降时间基本上等于从下一个激活的驱动级到在之后激活的驱动级的边沿上升时间和/或下降时间的差值 。

公开(公告)号：US06700426B2

公开(公告)日：2004-03-02

申请号：US10302864

申请日：2002-11-25

申请人： Martin Brox ,  Bernd Klehn ,  Joachim Schnabel

发明人： Martin Brox ,  Bernd Klehn ,  Joachim Schnabel

IPC分类号： H03L500

CPC分类号： H02M3/07 ,  G11C5/145

摘要： Programmable voltage pump for producing an output voltage includes a trim input configured to set the output voltage, an output configured to emit the output voltage therefrom, and an activation/deactivation input configured to at least one of activate and deactivate the voltage pump. The activation/deactivation input includes a switch connected to the output, the switch configured to selectively connect a network to ground, the network being connected to the output.

摘要翻译： 用于产生输出电压的可编程电压泵包括配置为设置输出电压的调整输入，被配置为从其发射输出电压的输出以及被配置为激活和去激活电压泵中的至少一个的激活/去激活输入。 激活/去激活输入包括连接到输出的交换机，交换机被配置为选择性地将网络连接到地，网络连接到输出。

公开(公告)号：US06971039B2

公开(公告)日：2005-11-29

申请号：US10075539

申请日：2002-02-14

申请人： Gunnar Krause ,  Sebastian Kuhne ,  Bernd Klehn

发明人： Gunnar Krause ,  Sebastian Kuhne ,  Bernd Klehn

IPC分类号： G11C7/10 ,  G11C7/22 ,  G11C11/4093 ,  G06F5/00

CPC分类号： G11C7/1084 ,  G11C7/1012 ,  G11C7/1051 ,  G11C7/1066 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/22 ,  G11C11/4093

摘要： A memory module is described which, externally, has the functionality of DDR SDRAMs and contains two groups of conventional SDRAMs. A conversion device provides for the conversion of clock signals, commands, and data. The conversion device contains a changeover switch, a delay locked loop and buffer memory for addresses and commands and also for the data, which are driven in a suitable manner by the delay locked loop.

摘要翻译： 描述了一种存储器模块，其在外部具有DDR SDRAM的功能并且包含两组常规SDRAM。 转换装置提供时钟信号，命令和数据的转换。 转换装置包含用于地址和命令的转换开关，延迟锁定环路和缓冲存储器，并且还包括以适当方式由延迟锁定环路驱动的数据。

公开(公告)号：US07127553B2

公开(公告)日：2006-10-24

申请号：US10717337

申请日：2003-11-19

申请人： Alexander Benedix ,  Georg Braun ,  Bernd Klehn

发明人： Alexander Benedix ,  Georg Braun ,  Bernd Klehn

IPC分类号： H01L27/108

CPC分类号： G06F11/3409

摘要： A configuration for executing data processing processes has an operating system and various system resources that are accessed by the operating system using an access strategy for the execution of system processes. When there are different applications, different access strategies to the system resources are used. A method is also provided for determining the optimum access strategy to the system resources.

摘要翻译： 用于执行数据处理过程的配置具有由操作系统使用用于执行系统进程的访问策略来访问的操作系统和各种系统资源。 当有不同的应用程序时，使用与系统资源不同的访问策略。 还提供了一种用于确定对系统资源的最佳访问策略的方法。

公开(公告)号：US07113024B2

公开(公告)日：2006-09-26

申请号：US10202914

申请日：2002-07-24

申请人： Franz Freimuth ,  Bernd Klehn ,  Ulrich Menczigar

发明人： Franz Freimuth ,  Bernd Klehn ,  Ulrich Menczigar

IPC分类号： G05F1/10 ,  G05F3/02

CPC分类号： G05F1/465

摘要： The invention relates to a circuit module with high-frequency input/output interfaces, and in particular to a circuit realized on a chip, principally a monolithic integrated circuit having a phase-regulated circuit which is fed by externally applied voltages and an internal operating voltage generated on the basis of a trimmable internal reference voltage. According to the invention, each further internal operating voltage is derived from an individual reference voltage on the basis of an external voltage. An adjusting circuit is provided which adjusts the individual reference voltage using the trimmable internal reference voltage and then freezes it.

公开(公告)号：US06635947B2

公开(公告)日：2003-10-21

申请号：US09934979

申请日：2001-08-21

申请人： Alexander Benedix ,  Georg Braun ,  Helmut Fischer ,  Bernd Klehn ,  Sebastian Kuhne

发明人： Alexander Benedix ,  Georg Braun ,  Helmut Fischer ,  Bernd Klehn ,  Sebastian Kuhne

IPC分类号： H01L2900

CPC分类号： G11C11/16 ,  H01L43/08

摘要： A monolithically integrable inductor containing a layer sequence of conductive layers and insulating layers that are stacked mutually alternately above one another is described. The conductive layers are configured in such a way that they form a coil-type structure around a central region, in which giant magnetic resistance materials can be provided.