摘要:
An integrated in situ oxide etch process particularly useful for a counterbore dual-damascene structure over copper having in one inter-layer dielectric level a lower nitride stop layer, a lower oxide dielectric, a lower nitride stop layer, an upper oxide dielectric layer, and an anti-reflective coating (ARC). The process is divided into a counterbore etch and a trench etch with photolithography for each, and each step is preferably performed in a high-density plasma reactor having an inductively coupled plasma source primarily generating the plasma and a capacitively coupled pedestal supporting the wafer and producing the bias power. The counterbore etch preferably includes at least four substeps of opening the ARC, etching through the upper oxide and nitride layers, selectively etching the lower oxide layer but stopping on the lower nitride layer, and a post-etch treatment for removing residue. The trench etch preferably includes the five substeps of opening the ARC, etching through the upper oxide layer but stopping on the upper nitride layers, a first post-etch treatment for removing residue, a nitride removal of the exposed portions of the upper and lower nitride layers, and a second post-etch treatment for remaining further residues. The oxide etches selective to nitride are accomplished using a fluorocarbon chemistry with high bias and a high temperature for a silicon-based scavenger for fluorine placed next to the plasma. The nitride etches and removal are accomplished by adding an oxygen-containing gas to a fluorocarbon. The final nitride removal is accomplished with very low bias power to increase selectivity to nitride and reduce sputtering of the underlying copper. The post-etch treatments are oxygen plasmas with zero bias power.
摘要:
A dielectric etch process applicable etching a dielectric layer with an underlying stop layer. It is particularly though not necessarily applicable to forming a dual-damascene interconnect structure by a counterbore process, in which a deep via is etched prior to the formation of a trench connecting two of more vias. A single metallization fills the dual-damascene structure. The substrate is formed with a lower stop layer, a lower dielectric layer, an upper stop layer, and an upper dielectric layer. For example, the dielectric layers may be silicon dioxide, and the stop layers, silicon nitride. The initial deep via etch includes at least two substeps. A first substep includes a non-selective etch through the upper stop layer followed by a second substep of selectively etching through the lower dielectric layer and stopping on the lower stop layer. The first substep may be preceded by yet another substep including a selective etch part ways through the upper dielectric layer. For the oxide/nitride compositions, the selective etch is based on a fluorocarbon and argon chemistry, preferably with a lean etchant of CHF3 combined with a polymer former, such as C2F6, C4F8, or CH2F2, and the non-selective etch includes a fluorocarbon or hydrocarbon, argon and an oxygen-containing gas, such as CO. The counterbore etch is preferably performed in a high-density plasma reactor which allows the plasma source region to be powered separately from a sheath bias located adjacent to the wafer pedestal.
摘要翻译:电介质蚀刻工艺可以用下面的停止层蚀刻电介质层。 特别地,不一定适用于通过沉孔工艺形成双镶嵌互连结构,其中在形成连接两个更多通孔的沟槽之前蚀刻深通孔。 单一的金属化填充了双镶嵌结构。 衬底形成有下停止层,下介电层,上阻挡层和上电介质层。 例如,电介质层可以是二氧化硅,并且阻挡层,氮化硅。 初始深通孔蚀刻包括至少两个子步骤。 第一子步骤包括通过上停止层的非选择性蚀刻,然后是选择性蚀刻穿过下介电层并停止在下停止层上的第二子步骤。 第一子步骤之前可以有另一子步骤,其中包括通过上电介质层的选择性蚀刻部分。 对于氧化物/氮化物组合物,选择性蚀刻基于碳氟化合物和氩气化学,优选用与聚合物形成剂如C 2 F 6,C 4 F 8或CH 2 F 2结合的CHF 3的贫蚀刻剂,并且非选择性蚀刻包括碳氟化合物 或烃,氩气和含氧气体,例如CO。沉孔蚀刻优选在高密度等离子体反应器中进行,其允许等离子体源区域与位于晶片基座附近的护套偏压分开供电。
摘要:
A dielectric etch process particularly applicable to forming a dual-damascene interconnect structure by a counterbore process, in which a deep via is etched prior to the formation of a trench connecting two of more vias. A single metallization fills the dual-damascene structure. The substrate is formed with a lower stop layer, a lower dielectric layer, an upper stop layer, and an upper dielectric layer. For example, the dielectric layers may be silicon dioxide, and the stop layers, silicon nitride. The initial deep via etch includes at least two substeps. A first substep includes a non-selective etch through the upper stop layer followed by a second substep of selectively etching through the lower dielectric layer and stopping on the lower stop layer. The first substep may be preceded by yet another substep including a selective etch part ways through the upper dielectric layer. For the oxide/nitride compositions, the selective etch is based on a fluorocarbon and argon chemistry, preferably with a lean etchant of CHF3 combined with a polymer former, such as C2F6, C4F8, or CH2F2, and the non-selective etch includes a fluorocarbon or hydrocarbon, argon and an oxygen-containing gas, such as CO. The counterbore etch is preferably performed in a high-density plasma reactor which allows the plasma source region to be powered separately from a sheath bias located adjacent to the wafer pedestal.
摘要翻译:特别适用于通过沉孔工艺形成双镶嵌互连结构的电介质蚀刻工艺,其中在形成连接两个更多通孔的沟槽之前蚀刻深通孔。 单一的金属化填充了双镶嵌结构。 衬底形成有下停止层,下介电层,上阻挡层和上电介质层。 例如,电介质层可以是二氧化硅,并且阻挡层,氮化硅。 初始深通孔蚀刻包括至少两个子步骤。 第一子步骤包括通过上停止层的非选择性蚀刻,然后是选择性蚀刻穿过下介电层并停止在下停止层上的第二子步骤。 第一子步骤之前可以有另一子步骤,其中包括通过上电介质层的选择性蚀刻部分。 对于氧化物/氮化物组合物,选择性蚀刻基于碳氟化合物和氩气化学,优选用与聚合物形成剂如C 2 F 6,C 4 F 8或CH 2 F 2结合的CHF 3的贫蚀刻剂,并且非选择性蚀刻包括碳氟化合物 或烃,氩气和含氧气体,例如CO。沉孔蚀刻优选在高密度等离子体反应器中进行,其允许等离子体源区域与位于晶片基座附近的护套偏压分开供电。
摘要:
The invention discloses a security configuration verification device for performing a security configuration verification on a network device, which comprises: one or more preconfigured scanning policies; a scanning policy generator, which selects a scanning policy from the one or more preconfigured scanning policies to generate a new scanning policy corresponding to the network device; and a scanner, which performs the security scanning on the network device with the generated new scanning policy and thereby performs the security configuration verification. The invention also discloses a corresponding security configuration verification method and a network system employing the verification device.
摘要:
Method and apparatus for etching a metal layer disposed on a substrate, such as a photolithographic reticle, are provided. In one aspect, a method is provided for processing a substrate including positioning a substrate having a metal layer disposed on an optically transparent material in a processing chamber, introducing a processing gas processing gas comprising an oxygen containing gas, a chlorine containing gas, and a chlorine-free halogen containing gas, and optionally, an inert gas, into the processing chamber, generating a plasma of the processing gas in the processing chamber, and etching exposed portions of the metal layer disposed on the substrate.
摘要:
Certain biomarkers and biomarker combinations are useful in a qualifying ischaemic heart disease status in a patient. A diagnostic methodology employing these biomarkers and combinations can distinguish between ischaemic heart disease and normal, as well as between cases of severe myocardial infarction versus mild myocardial infarction.
摘要:
Methods and apparatus for preparing data for encrypted transmission. According to the current invention, a data bitstream may be processed to create side information. After extracting, generating and/or acquiring the side data, some or all of the data bitstream may be encrypted and then combined to create a combined data bitstream, ready for transmission. Subsequently, the combined data bitstream may be transmitted over a network. By processing a data bitstream to extract metadata about the bitstream before encrypting the data, some processing such as splicing, bit rate switching and/or statistical multiplexing done after encryption may be executed without requiring costly de-encryption/re-encryption steps based, in part, on inspecting the contents of the side data. The bitstream may represent video, audio, image or other data types. In some examples according to the current invention, a combined data bitstream may comprise multiple bitstreams, each at a different bit rate.
摘要:
The invention relates to pseudolaric acid-B derivatives of general formula (I), wherein (a) R1 is cyano, heterocyclyl, COXR′ or CON(R″)2, wherein X is O or NH, R′ is H, cycloalkyl, alkyl, heterocyclic alkyl or arylalkyl, each R″ is independently alkyl, cycloalkyl or heterocyclicalkyl; (b) R2 is H, alkylacyl, arylalkylacyl, arylacyl or heterocyclylacyl; (c) R3 is COXY, amino or halogen, wherein X is O or NH, Y is H, NH2, hydroxy, alkyl, cycloalkyl, heterocyclicalkyl, hetroatom-substituted alkyl, tertiary amino-substituted ammonioalkyl, aryl, arylalkyl or polyhydroxyalkyl. The invention also relates to processes for preparing such derivatives and antitumor or antifungal pharmaceutical compositions containing the same.
摘要:
A high plasma density etch process for etching an oxygen-containing layer overlying a non-oxygen containing layer on a workpiece in a plasma reactor chamber, by providing a chamber ceiling overlying the workpiece and containing a semiconductor material, supplying into the chamber a process gas containing etchant precursor species, polymer precursor species and hydrogen, applying plasma source power into the chamber, and cooling the ceiling to a temperature range at or below about 150 degrees C. The etchant and polymer precursor species contain fluorine, and the chamber ceiling semiconductor material includes a fluorine scavenger precursor material. Preferably, the process gas includes at least one of CHF3 and CH2F2. Preferably, the process gas further includes a species including an inert gas, such as HeH2 or Ar. If the chamber is of the type including a heated fluorine scavenger precursor material, this material is heated to well above the polymer condensation temperature, while the ceiling is cooled. In some cases, the plasma source power applicator is an inductive antenna overlying the semiconductor ceiling, and the ceiling has a cooling/heating apparatus contacting the ceiling through semiconductor rings. The inductive antenna in this case constitutes inductive elements between adjacent ones of the semiconductor rings.