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    Flip chip substrate structure and the method for manufacturing the same
    4.
    发明申请
    Flip chip substrate structure and the method for manufacturing the same 审中-公开
    倒装芯片基板结构及其制造方法

    公开(公告)号：US20080060838A1

    公开(公告)日：2008-03-13

    申请号：US11519896

    申请日：2006-09-13

    申请人： Bo-Wei Chen ,  Hsien-Shou Wang ,  Shih-Ping Hsu

    发明人： Bo-Wei Chen ,  Hsien-Shou Wang ,  Shih-Ping Hsu

    IPC分类号： H05K1/11 ,  H01R12/04

    CPC分类号： H05K3/4682 ,  H01L21/4857 ,  H01L21/68 ,  H01L23/49822 ,  H01L2924/0002 ,  H05K3/205 ,  H05K3/243 ,  H05K3/28 ,  H05K3/4007 ,  H05K2201/0367 ,  H05K2201/09481 ,  H05K2201/09563 ,  H05K2201/096 ,  H05K2201/099 ,  H05K2203/0384 ,  H01L2924/00

    摘要： A flip chip substrate structure and a method to fabricate thereof are disclosed. The structure comprises a build up structure, a first solder mask and a second solder mask. Plural first and second electrical contact pads are formed on the first and second surface of the build up structure, respectively. A first solder mask having plural openings is formed on the first surface of the build up structure, and the openings expose the first electrical contact pads, wherein the aperture of the openings of the first solder mask are equal to the outer diameter of the first electrical contact pads. A second solder mask having plural openings is formed on the second surface of the build up structure, and the openings expose the second electrical contact pads, wherein the aperture of the openings of the second solder mask are smaller than the outer diameter of the second electrical contact pads.

    摘要翻译： 公开了倒装芯片基板结构及其制造方法。 该结构包括建立结构，第一焊接掩模和第二焊接掩模。 分别在堆积结构的第一和第二表面上形成多个第一和第二电接触焊盘。 具有多个开口的第一焊料掩模形成在构建结构的第一表面上，并且开口暴露第一电接触焊盘，其中第一焊接掩模的开口的孔径等于第一电接触焊盘的外径 接触垫 具有多个开口的第二焊料掩模形成在构建结构的第二表面上，并且开口暴露第二电接触焊盘，其中第二焊接掩模的开口的孔径小于第二电接触焊盘的外径 接触垫

    Method for fabricating a flip chip substrate structure
    6.
    发明授权
    Method for fabricating a flip chip substrate structure 有权
    制造倒装芯片基板结构的方法

    公开(公告)号：US07820233B2

    公开(公告)日：2010-10-26

    申请号：US11527632

    申请日：2006-09-27

    申请人： Bo-Wei Chen ,  Hsien-Shou Wang ,  Shih-Ping Hsu

    发明人： Bo-Wei Chen ,  Hsien-Shou Wang ,  Shih-Ping Hsu

    IPC分类号： B05D5/12

    CPC分类号： H05K3/4007 ,  C23C18/1605 ,  C23C18/165 ,  C23C18/31 ,  C25D5/022 ,  H01L21/486 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2924/0002 ,  H05K3/108 ,  H05K3/205 ,  H05K3/28 ,  H05K3/4644 ,  H05K2201/09472 ,  H05K2201/09481 ,  H05K2201/09563 ,  H05K2201/096 ,  H05K2203/0384 ,  H01L2924/00

    摘要： The present invention relates to a method to fabricate a flip chip substrate structure, which comprises: providing a carrier; forming a patterned resist layer on the surface of the carrier; forming sequentially a first metal layer, an etching-stop layer, and a second metal layer; removing the resist layer, forming a patterned first solder mask, and then forming at least one first circuit build up structure thereon; forming additionally a patterned second solder mask on the circuit build up structure; respectively removing the carrier, the first metal layer, and the etching-stop layer; and forming solder bumps on both sides of the circuit build up structure. The method increases integration and achieves the purpose of miniaturization. The method solves the problem of circuit layer multiplicity and process complexity.

    摘要翻译： 本发明涉及一种制造倒装芯片基板结构的方法，包括：提供载体; 在载体的表面上形成图案化的抗蚀剂层; 顺序地形成第一金属层，蚀刻停止层和第二金属层; 去除抗蚀剂层，形成图案化的第一焊料掩模，然后在其上形成至少一个第一电路堆积结构; 在电路构建结构上另外形成图案化的第二焊料掩模; 分别去除载体，第一金属层和蚀刻停止层; 以及在电路构建结构的两侧形成焊料凸块。 该方法增加了集成度，达到了小型化的目的。 该方法解决了电路层多重性和工艺复杂度的问题。

    Coreless package substrate with conductive structures
    7.
    发明授权
    Coreless package substrate with conductive structures 失效
    具有导电结构的无芯封装衬底

    公开(公告)号：US07626270B2

    公开(公告)日：2009-12-01

    申请号：US11583082

    申请日：2006-10-19

    申请人： Bo-Wei Chen ,  Hsien-Shou Wang ,  Shih-Ping Hsu

    发明人： Bo-Wei Chen ,  Hsien-Shou Wang ,  Shih-Ping Hsu

    IPC分类号： H01L23/48 ,  H05K7/00 ,  H05K1/03

    CPC分类号： H05K3/4682 ,  H01L21/4857 ,  H01L23/49822 ,  H01L2924/0002 ,  H05K1/113 ,  H05K3/205 ,  H05K3/243 ,  H05K3/28 ,  H05K2201/09563 ,  H05K2201/096 ,  H05K2203/0361 ,  H05K2203/0384 ,  H01L2924/00

    摘要： A method of manufacturing a coreless package substrate together with a conductive structure of the substrate is disclosed. The method can produce a coreless package substrate which comprises: at least a built-up structure having a first solder mask and a second solder mask, wherein a plurality of openings are formed in the first and second solder mask to expose the conductive pads of the built-up structure; and a plurality of solder bumps as well as solder layers formed on the conductive pads. Therefore, the invention can produce the coreless package substrate with high density of circuit layout, less manufacturing steps, and small size.

    摘要翻译： 公开了一种制造无芯封装衬底以及衬底的导电结构的方法。 该方法可以产生无芯封装衬底，其包括：至少具有第一焊料掩模和第二焊料掩模的堆积结构，其中在第一和第二焊料掩模中形成多个开口以暴露出 建筑结构; 以及形成在导电焊盘上的多个焊料凸块以及焊料层。 因此，本发明可以生产具有高密度电路布局，较少制造步骤和小尺寸的无芯封装衬底。

    Method for fabricating a flip chip substrate structure
    9.
    发明申请
    Method for fabricating a flip chip substrate structure 有权
    制造倒装芯片基板结构的方法

    公开(公告)号：US20080075836A1

    公开(公告)日：2008-03-27

    申请号：US11527632

    申请日：2006-09-27

    申请人： Bo-Wei Chen ,  Hsien-Shou Wang ,  Shih-Ping Hsu

    发明人： Bo-Wei Chen ,  Hsien-Shou Wang ,  Shih-Ping Hsu

    IPC分类号： B05D5/12 ,  C23C26/00 ,  B05D5/00

    CPC分类号： H05K3/4007 ,  C23C18/1605 ,  C23C18/165 ,  C23C18/31 ,  C25D5/022 ,  H01L21/486 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2924/0002 ,  H05K3/108 ,  H05K3/205 ,  H05K3/28 ,  H05K3/4644 ,  H05K2201/09472 ,  H05K2201/09481 ,  H05K2201/09563 ,  H05K2201/096 ,  H05K2203/0384 ,  H01L2924/00

    摘要： The present invention relates to a method to fabricate a flip chip substrate structure, which comprises: providing a carrier; forming a patterned resist layer on the surface of the carrier; forming sequentially a first metal layer, an etching-stop layer, and a second metal layer; removing the resist layer, forming a patterned first solder mask, and then forming at least one first circuit build up structure thereon; forming additionally a patterned second solder mask on the circuit build up structure; respectively removing the carrier, the first metal layer, and the etching-stop layer; and forming solder bumps on both sides of the circuit build up structure. The method increases integration and achieves the purpose of miniaturization. The method solves the problem of circuit layer multiplicity and process complexity.

    摘要翻译： 本发明涉及一种制造倒装芯片基板结构的方法，包括：提供载体; 在载体的表面上形成图案化的抗蚀剂层; 顺序地形成第一金属层，蚀刻停止层和第二金属层; 去除抗蚀剂层，形成图案化的第一焊料掩模，然后在其上形成至少一个第一电路堆积结构; 在电路构建结构上另外形成图案化的第二焊料掩模; 分别去除载体，第一金属层和蚀刻停止层; 以及在电路构建结构的两侧形成焊料凸块。 该方法增加了集成度，达到了小型化的目的。 该方法解决了电路层多重性和工艺复杂度的问题。