Flip chip substrate structure and the method for manufacturing the same
    3.
    发明申请
    Flip chip substrate structure and the method for manufacturing the same 审中-公开
    倒装芯片基板结构及其制造方法

    公开(公告)号:US20080060838A1

    公开(公告)日:2008-03-13

    申请号:US11519896

    申请日:2006-09-13

    IPC分类号: H05K1/11 H01R12/04

    摘要: A flip chip substrate structure and a method to fabricate thereof are disclosed. The structure comprises a build up structure, a first solder mask and a second solder mask. Plural first and second electrical contact pads are formed on the first and second surface of the build up structure, respectively. A first solder mask having plural openings is formed on the first surface of the build up structure, and the openings expose the first electrical contact pads, wherein the aperture of the openings of the first solder mask are equal to the outer diameter of the first electrical contact pads. A second solder mask having plural openings is formed on the second surface of the build up structure, and the openings expose the second electrical contact pads, wherein the aperture of the openings of the second solder mask are smaller than the outer diameter of the second electrical contact pads.

    摘要翻译: 公开了倒装芯片基板结构及其制造方法。 该结构包括建立结构,第一焊接掩模和第二焊接掩模。 分别在堆积结构的第一和第二表面上形成多个第一和第二电接触焊盘。 具有多个开口的第一焊料掩模形成在构建结构的第一表面上,并且开口暴露第一电接触焊盘,其中第一焊接掩模的开口的孔径等于第一电接触焊盘的外径 接触垫 具有多个开口的第二焊料掩模形成在构建结构的第二表面上,并且开口暴露第二电接触焊盘,其中第二焊接掩模的开口的孔径小于第二电接触焊盘的外径 接触垫

    Flip-chip package substrate and a method for fabricating the same
    7.
    发明授权
    Flip-chip package substrate and a method for fabricating the same 有权
    倒装芯片封装基板及其制造方法

    公开(公告)号:US07867888B2

    公开(公告)日:2011-01-11

    申请号:US11808028

    申请日:2007-06-06

    申请人: Hsien-Shou Wang

    发明人: Hsien-Shou Wang

    IPC分类号: H01L23/532 H01L21/44

    摘要: The present invention provides a flip-chip package substrate and a method for fabricating a flip-chip package substrate comprising a circuit build-up structure, which comprises at least a dielectric layer and at least a circuit layer, wherein each dielectric layer comprises a first surface and a second surface, plural vias are formed in the first surface, the circuit layer is formed on the first surface and in the vias to electrically connect to another circuit layer disposed under the dielectric layer; a metal layer embedded in the exposed second surface of the circuit build-up structure without protruding the exposed second surface and connected to the circuit layer; and two solder masks disposed on the exposed first surface and the exposed second surface of the circuit build-up structure, wherein the solder masks have plural openings to separately expose part of the circuit layer and the metal layer functioning as conductive pads.

    摘要翻译: 本发明提供了一种倒装芯片封装基板和一种用于制造倒装芯片封装基板的方法,该封装基板包括至少包括介电层和至少电路层的电路组合结构,其中每个电介质层包括第一 表面和第二表面,在第一表面中形成多个通孔,电路层形成在第一表面和通孔中,以电连接到设置在电介质层下方的另一个电路层; 嵌入在电路堆积结构的暴露的第二表面中的金属层,而不突出暴露的第二表面并连接到电路层; 以及设置在暴露的第一表面和电路堆积结构的暴露的第二表面上的两个焊接掩模,其中焊料掩模具有多个开口以分别暴露电路层的一部分和用作导电焊盘的金属层。

    Method for fabricating a flip chip substrate structure
    10.
    发明授权
    Method for fabricating a flip chip substrate structure 有权
    制造倒装芯片基板结构的方法

    公开(公告)号:US07820233B2

    公开(公告)日:2010-10-26

    申请号:US11527632

    申请日:2006-09-27

    IPC分类号: B05D5/12

    摘要: The present invention relates to a method to fabricate a flip chip substrate structure, which comprises: providing a carrier; forming a patterned resist layer on the surface of the carrier; forming sequentially a first metal layer, an etching-stop layer, and a second metal layer; removing the resist layer, forming a patterned first solder mask, and then forming at least one first circuit build up structure thereon; forming additionally a patterned second solder mask on the circuit build up structure; respectively removing the carrier, the first metal layer, and the etching-stop layer; and forming solder bumps on both sides of the circuit build up structure. The method increases integration and achieves the purpose of miniaturization. The method solves the problem of circuit layer multiplicity and process complexity.

    摘要翻译: 本发明涉及一种制造倒装芯片基板结构的方法,包括:提供载体; 在载体的表面上形成图案化的抗蚀剂层; 顺序地形成第一金属层,蚀刻停止层和第二金属层; 去除抗蚀剂层,形成图案化的第一焊料掩模,然后在其上形成至少一个第一电路堆积结构; 在电路构建结构上另外形成图案化的第二焊料掩模; 分别去除载体,第一金属层和蚀刻停止层; 以及在电路构建结构的两侧形成焊料凸块。 该方法增加了集成度,达到了小型化的目的。 该方法解决了电路层多重性和工艺复杂度的问题。