公开(公告)号：US06185081B2

公开(公告)日：2001-02-06

申请号：US09345552

申请日：1999-06-30

申请人： Bogdan M. Simion ,  Yingjian Chen ,  Mark S. Miller

发明人： Bogdan M. Simion ,  Yingjian Chen ,  Mark S. Miller

IPC分类号： G11B539

CPC分类号： B82Y25/00 ,  B82Y10/00 ,  G01R33/093 ,  G11B5/3903 ,  G11B5/3932 ,  G11B2005/3996

摘要： Bias layers for a magnetoresistive (MR) sensor have an in-plane easy axis of magnetization for providing a longitudinal bias to MR layers. The bias layers include cobalt (Co), and are formed on various underlayers having crystalline structures that encourage an in-plane alignment of the C-axis of that Co. Preferred underlayers include nickel aluminum (NiAl) and magnesium oxide (MgO), and an interlayer containing chromium (Cr) may be interposed between a bias layer and an underlayer.

摘要翻译： 用于磁阻（MR）传感器的偏置层具有面内容易的磁化轴，以向MR层提供纵向偏置。 偏置层包括钴（Co），并且形成在具有促进该Co的C轴的面内对准的结晶结构的各种底层上。优选的底层包括镍铝（NiAl）和氧化镁（MgO），以及 可以在偏置层和底层之间插入含有铬（Cr）的中间层。

公开(公告)号：US20110247852A1

公开(公告)日：2011-10-13

申请号：US12755665

申请日：2010-04-07

申请人： Bogdan M. Simion

发明人： Bogdan M. Simion

IPC分类号： H05K5/06 ,  H05K13/00

CPC分类号： H01L21/563 ,  B29C2791/006 ,  H01L24/27 ,  H01L24/743 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2924/01029 ,  H01L2924/01322 ,  H01L2924/14 ,  Y10T29/4998 ,  H01L2924/00

摘要： The present disclosure relate to the field of depositing an underfill material between a microelectronic die and a substrate for flip-chip packages. In at least one embodiment, differential pressure is used to meter the underfill material during the underfill deposition process.

摘要翻译： 本公开涉及在微电子管芯和用于倒装芯片封装的衬底之间沉积底部填充材料的领域。 在至少一个实施例中，在底部填充沉积过程中使用差压来计量底部填充材料。

公开(公告)号：US06989972B1

公开(公告)日：2006-01-24

申请号：US10261119

申请日：2002-09-30

申请人： Kroum Stoev ,  Mathew Gibbons ,  Francis Liu ,  Bogdan M. Simion ,  Aparna C. Vadde ,  Jing Zhang ,  Yiming Huai ,  Marcos M. Lederman

发明人： Kroum Stoev ,  Mathew Gibbons ,  Francis Liu ,  Bogdan M. Simion ,  Aparna C. Vadde ,  Jing Zhang ,  Yiming Huai ,  Marcos M. Lederman

IPC分类号： G11B5/39

CPC分类号： G11B5/3932

摘要： Magnetoresistive (MR) sensors have leads that overlap a MR structure and distribute current to the MR structure so that the current is not concentrated in small portions of the leads. An electrically resistive capping layer can be formed between the leads and the MR structure to distribute the current. The leads can include resistive layers and conductive layers, the resistive layers having a thickness-to-resistivity ratio that is greater than that of each of the conductive layers. The resistive layers may protect the conductive layers during MR structure etching, so that the leads have broad layers of electrically conductive material for connection to MR structures. The broad leads conduct heat better than the read gap material that they replace, further reducing the temperature at the connection between the leads and the MR structure.

摘要翻译： 磁阻（MR）传感器具有与MR结构重叠并且将电流分配到MR结构的引线，使得电流不集中在引线的小部分中。 可以在引线和MR结构之间形成电阻覆盖层以分布电流。 引线可以包括电阻层和导电层，电阻层的厚度 - 电阻率比大于每个导电层的厚度 - 电阻率比。 电阻层可以在MR结构蚀刻期间保护导电层，使得引线具有用于连接到MR结构的宽的导电材料层。 宽引线比它们所替代的读取间隙材料更好地传导热量，进一步降低引线与MR结构之间的连接处的温度。

公开(公告)号：US07829195B2

公开(公告)日：2010-11-09

申请号：US11618905

申请日：2006-12-31

申请人： Bogdan M. Simion

发明人： Bogdan M. Simion

IPC分类号： B32B5/02

CPC分类号： H01L23/3735 ,  F28F2013/006 ,  H01L21/4871 ,  H01L23/3675 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01327 ,  H01L2924/16251 ,  H01L2924/00 ,  H01L2224/0401

摘要： The formation of electronic assemblies including a heat spreader coupled to a die through a thermal interface material formed from an indium preform, is described. One embodiment relates to a method including providing a preform comprising indium, the preform including an indium oxide layer thereon. The method also includes exposing the preform to fluorine so that part of the indium oxide layer is transformed into an indium oxy-fluoride. The method may also include, after the exposing the preform to fluorine so that part of the indium oxide layer is transformed into an indium oxy-fluoride, positioning the preform between a die and a heat sink, and applying pressure to and heating the preform positioned between the die and the heat sink so that reflow occurs and a bond is formed between the die and the heat sink.

摘要翻译： 描述了包括通过由铟预成型件形成的热界面材料耦合到管芯的散热器的电子组件的形成。 一个实施例涉及一种包括提供包含铟的预制件的方法，所述预制件在其上包括氧化铟层。 该方法还包括将预成型件暴露于氟中，使得氧化铟层的一部分转化为氧氟化铟。 该方法还可以包括在将预成型坯暴露于氟之后，使得氧化铟层的一部分转化为氟化铟铟，将预型件定位在模具和散热器之间，并将预压件施加压力并加热 在模具和散热器之间，使得回流发生并且在管芯和散热器之间形成结合。

公开(公告)号：US08211501B2

公开(公告)日：2012-07-03

申请号：US12907006

申请日：2010-10-18

申请人： Bogdan M. Simion

发明人： Bogdan M. Simion

IPC分类号： C23C16/40 ,  H05H1/24

CPC分类号： H01L23/3735 ,  F28F2013/006 ,  H01L21/4871 ,  H01L23/3675 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01327 ,  H01L2924/16251 ,  H01L2924/00 ,  H01L2224/0401

摘要： The formation of electronic assemblies including a heat spreader coupled to a die through a thermal interface material formed from an indium preform, is described. One embodiment relates to a method including providing a preform comprising indium, the preform including an indium oxide layer thereon. The method also includes exposing the preform to fluorine so that part of the indium oxide layer is transformed into an indium oxy-fluoride. The method may also include, after the exposing the preform to fluorine so that part of the indium oxide layer is transformed into an indium oxy-fluoride, positioning the preform between a die and a heat sink, and applying pressure to and heating the preform positioned between the die and the heat sink so that reflow occurs and a bond is formed between the die and the heat sink.

摘要翻译： 描述了包括通过由铟预成型件形成的热界面材料耦合到管芯的散热器的电子组件的形成。 一个实施例涉及一种包括提供包含铟的预制件的方法，所述预制件在其上包括氧化铟层。 该方法还包括将预成型件暴露于氟中，使得氧化铟层的一部分转化为氧氟化铟。 该方法还可以包括在将预成型坯暴露于氟之后，使得氧化铟层的一部分转化为氟化铟铟，将预型件定位在模具和散热器之间，并将预压件施加压力并加热 在模具和散热器之间，使得回流发生并且在管芯和散热器之间形成结合。

公开(公告)号：US20110248046A1

公开(公告)日：2011-10-13

申请号：US12756726

申请日：2010-04-08

申请人： Bogdan M. Simion ,  Curtis S. White ,  Sung-Won Moon

发明人： Bogdan M. Simion ,  Curtis S. White ,  Sung-Won Moon

IPC分类号： B67D7/82

CPC分类号： B05C11/1042 ,  B05C5/0225 ,  H01L21/6715

摘要： The present disclosure relate to the field of depositing an underfill material between a microelectronic die and a substrate for flip-chip packages with an underfill material dispenser. In at least one embodiment, an underfill material dispenser may include a heater having a plurality of conduits. Other embodiments of the present disclosure may further include multiple dispense needle configurations, angled dispense nozzle exit conduits, conical nozzle exit conduits, and satellite traps.

摘要翻译： 本公开涉及在具有底部填充材料分配器的倒装芯片封装的微电子管芯和衬底之间沉积底部填充材料的领域。 在至少一个实施例中，底部填充材料分配器可以包括具有多个导管的加热器。 本公开的其他实施例还可以包括多个分配针配置，成角度的分配喷嘴出口导管，锥形喷嘴出口导管和卫星陷阱。

公开(公告)号：US20140084478A1

公开(公告)日：2014-03-27

申请号：US13627487

申请日：2012-09-26

申请人： Bogdan M. Simion

发明人： Bogdan M. Simion

IPC分类号： H01L23/48 ,  B29B13/00 ,  H01L21/50

CPC分类号： H01L25/50 ,  B29C37/0075 ,  B29C43/28 ,  H01L21/4853 ,  H01L21/565 ,  H01L21/566 ,  H01L21/76817 ,  H01L21/76897 ,  H01L23/3157 ,  H01L23/49811 ,  H01L23/49833 ,  H01L23/5226 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/92 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/18 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16238 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/92125 ,  H01L2224/97 ,  H01L2225/06517 ,  H01L2225/06555 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1088 ,  H01L2924/12042 ,  H01L2924/1432 ,  H01L2924/1434 ,  H01L2924/15321 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2224/81 ,  H01L2924/00

摘要： Embodiments of the present disclosure are directed towards a mold chase for integrated circuit package assembly and associated techniques and configurations. In one embodiment, a method includes receiving a package substrate, the package substrate including a first die mounted on the package substrate by a plurality of first interconnect structures, and a plurality of second interconnect structures disposed on the package substrate and configured to route electrical signals of a second die, protecting a top surface of individual interconnect structures of the plurality of second interconnect structures from deposition of a mold material, and depositing the mold material on the package substrate between the individual interconnect structures of the plurality of second interconnect structures. Other embodiments may be described and/or claimed.

摘要翻译： 本公开的实施例涉及用于集成电路封装组件和相关技术和配置的模具追逐。 在一个实施例中，一种方法包括接收封装衬底，所述封装衬底包括通过多个第一互连结构安装在所述封装衬底上的第一管芯，以及设置在所述封装衬底上并被配置为布置电信号的多个第二互连结构 保护所述多个第二互连结构中的各个互连结构的顶表面不会沉积模具材料，以及将所述模具材料沉积在所述多个第二互连结构的各个互连结构之间的所述封装衬底上。 可以描述和/或要求保护其他实施例。

公开(公告)号：US08366982B2

公开(公告)日：2013-02-05

申请号：US12755665

申请日：2010-04-07

申请人： Bogdan M. Simion

发明人： Bogdan M. Simion

IPC分类号： B29C70/72 ,  B29C45/14 ,  H01L21/56

CPC分类号： H01L21/563 ,  B29C2791/006 ,  H01L24/27 ,  H01L24/743 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2924/01029 ,  H01L2924/01322 ,  H01L2924/14 ,  Y10T29/4998 ,  H01L2924/00

摘要： The present disclosure relate to the field of depositing an underfill material between a microelectronic die and a substrate for flip-chip packages. In at least one embodiment, differential pressure is used to meter the underfill material during the underfill deposition process.

摘要翻译： 本公开涉及在微电子管芯和用于倒装芯片封装的衬底之间沉积底部填充材料的领域。 在至少一个实施例中，在底部填充沉积过程中使用差压来计量底部填充材料。