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    Apparatus for depositing a thin film on a substrate
    1.
    发明申请
    Apparatus for depositing a thin film on a substrate 审中-公开
    用于在基板上沉积薄膜的装置

    公开(公告)号：US20060016396A1

    公开(公告)日：2006-01-26

    申请号：US11179136

    申请日：2005-07-12

    申请人： Bong-Jin Kuh ,  Horii Hideki ,  Soon-Oh Park ,  Jang-Eun Lee ,  Yong-Ho Ha

    发明人： Bong-Jin Kuh ,  Horii Hideki ,  Soon-Oh Park ,  Jang-Eun Lee ,  Yong-Ho Ha

    IPC分类号： C23C16/00

    CPC分类号： C23C14/165 ,  C23C14/046 ,  C23C14/35 ,  C23C14/50

    摘要： An apparatus for depositing a thin film on a substrate includes a housing, a substrate support portion, a securing member, a heater, a target member and a plasma generator. The housing defines a process chamber. The substrate support portion is disposed in the process chamber to support the substrate. The securing member is adapted to non-electrically secure the substrate to the substrate support portion during performance of a process. The heater is provided to maintain the substrate supported by the substrate support portion at a process temperature. The target member faces the substrate support portion and includes materials to be deposited on the substrate. The plasma generator is adapted to excite a process gas supplied into the process chamber into a plasma state.

    摘要翻译： 用于在衬底上沉积薄膜的装置包括壳体，衬底支撑部分，固定构件，加热器，目标构件和等离子体发生器。 壳体限定了处理室。 衬底支撑部分设置在处理室中以支撑衬底。 固定构件适于在执行过程期间将基板非电气地固定到基板支撑部分。 提供加热器以将基板支撑部分支撑的基板保持在处理温度。 目标构件面向衬底支撑部分并且包括待沉积在衬底上的材料。 等离子体发生器适于将供应到处理室中的工艺气体激发成等离子体状态。

    Methods of forming multi-level cell of semiconductor memory
    6.
    发明授权
    Methods of forming multi-level cell of semiconductor memory 有权
    形成半导体存储器多级单元的方法

    公开(公告)号：US08187918B2

    公开(公告)日：2012-05-29

    申请号：US12587772

    申请日：2009-10-13

    申请人： Gyu-Hwan Oh ,  Hyeung-Geun An ,  Soon-Oh Park ,  Dong-Ho Ahn ,  Young-Lim Park

    发明人： Gyu-Hwan Oh ,  Hyeung-Geun An ,  Soon-Oh Park ,  Dong-Ho Ahn ,  Young-Lim Park

    IPC分类号： H01L21/06

    CPC分类号： H01L45/141 ,  H01L27/2409 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/144 ,  H01L45/1666 ,  H01L45/1683

    摘要： Provided is a method of forming a semiconductor memory cell in which in order to store two bits or more data in a memory cell, three or more bottom electrode contacts (BECs) and phase-change materials (GST) have a parallel structure on a single contact plug (CP) and set resistances are changed depending on thicknesses (S), lengths (L) or resistivities (ρ) of the three or more bottom electrode contacts, so that a reset resistance and three different set resistances enable data other than in set and reset states to be stored. Also, a method of forming a memory cell in which three or more phase-change materials (GST) have a parallel structure on a single bottom electrode contact, and the phase-change materials have different set resistances depending on composition ratio or type, so that four or more different resistances can be implemented is provided.

    摘要翻译： 提供了一种形成半导体存储单元的方法，其中为了在存储单元中存储两个或更多个数据，三个或更多个底部电极触点（BEC）和相变材料（GST）在单个存储单元上具有并联结构 接触插头（CP）和设定电阻根据三个或更多个底部电极触点的厚度（S），长度（L）或电阻率（＆rgr）而改变，因此复位电阻和三种不同的设定电阻使数据不能 在设置和复位状态下存储。 此外，形成其中三个或更多个相变材料（GST）在单个底部电极接触上具有平行结构的存储单元的方法，并且相变材料根据组成比或类型具有不同的设定电阻，因此 可以实现四个或更多个不同的电阻。

    Methods of forming multi-level cell of semiconductor memory
    7.
    发明申请
    Methods of forming multi-level cell of semiconductor memory 有权
    形成半导体存储器多级单元的方法

    公开(公告)号：US20100093130A1

    公开(公告)日：2010-04-15

    申请号：US12587772

    申请日：2009-10-13

    申请人： Gyu-Hwan Oh ,  Hyeong-Geun An ,  Soon-Oh Park ,  Dong-Ho Ahn ,  Young-Lim Park

    发明人： Gyu-Hwan Oh ,  Hyeong-Geun An ,  Soon-Oh Park ,  Dong-Ho Ahn ,  Young-Lim Park

    IPC分类号： H01L21/06

    CPC分类号： H01L45/141 ,  H01L27/2409 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/144 ,  H01L45/1666 ,  H01L45/1683

    摘要： Provided is a method of forming a semiconductor memory cell in which in order to store two bits or more data in a memory cell, three or more bottom electrode contacts (BECs) and phase-change materials (GST) have a parallel structure on a single contact plug (CP) and set resistances are changed depending on thicknesses (S), lengths (L) or resistivities (ρ) of the three or more bottom electrode contacts, so that a reset resistance and three different set resistances enable data other than in set and reset states to be stored. Also, a method of forming a memory cell in which three or more phase-change materials (GST) have a parallel structure on a single bottom electrode contact, and the phase-change materials have different set resistances depending on composition ratio or type, so that four or more different resistances can be implemented is provided.

    摘要翻译： 提供了一种形成半导体存储单元的方法，其中为了在存储单元中存储两个或更多个数据，三个或更多个底部电极触点（BEC）和相变材料（GST）在单个存储单元上具有并联结构 接触插头（CP）和设定电阻根据三个或更多个底部电极触点的厚度（S），长度（L）或电阻率（＆rgr）而改变，因此复位电阻和三种不同的设定电阻使数据不能 在设置和复位状态下存储。 此外，形成其中三个或更多个相变材料（GST）在单个底部电极接触上具有平行结构的存储单元的方法，并且相变材料根据组成比或类型具有不同的设定电阻，因此 可以实现四个或更多个不同的电阻。

    Method of forming a phase change material layer pattern and method of manufacturing a phase change memory device
    8.
    发明授权
    Method of forming a phase change material layer pattern and method of manufacturing a phase change memory device 有权
    形成相变材料层图案的方法和制造相变存储器件的方法

    公开(公告)号：US08865558B2

    公开(公告)日：2014-10-21

    申请号：US13543905

    申请日：2012-07-09

    申请人： Jeong-Hee Park ,  Soon-Oh Park ,  Jung-Hwan Park ,  Jin-Ho Oh

    发明人： Jeong-Hee Park ,  Soon-Oh Park ,  Jung-Hwan Park ,  Jin-Ho Oh

    IPC分类号： H01L47/00 ,  H01L45/00

    CPC分类号： H01L45/06 ,  H01L45/141 ,  H01L45/1683

    摘要： A method of forming a phase change material layer pattern includes forming a phase change material layer partially filling an opening through an insulating interlayer. A plasma treatment process is performed on the phase change material layer to remove an oxide layer on a surface of the phase change material layer. A heat treatment process is performed on the phase change material layer to remove a void or a seam in the phase change material layer, sufficiently filling the opening.

    摘要翻译： 形成相变材料层图案的方法包括：通过绝缘中间层形成部分填充开口的相变材料层。 在相变材料层上进行等离子体处理工艺以去除相变材料层的表面上的氧化物层。 在相变材料层上进行热处理工艺以去除相变材料层中的空隙或接缝，充分填充开口。

    Nonvolatile memory devices, nonvolatile memory cells and methods of manufacturing nonvolatile memory devices
    10.
    发明授权
    Nonvolatile memory devices, nonvolatile memory cells and methods of manufacturing nonvolatile memory devices 有权
    非易失性存储器件，非易失性存储器单元以及制造非易失性存储器件的方法

    公开(公告)号：US09343672B2

    公开(公告)日：2016-05-17

    申请号：US13442595

    申请日：2012-04-09

    申请人： Chan-Jin Park ,  Sun-Jung Kim ,  Soon-Oh Park ,  Hyun-Su Ju ,  Soo-Doo Chae

    发明人： Chan-Jin Park ,  Sun-Jung Kim ,  Soon-Oh Park ,  Hyun-Su Ju ,  Soo-Doo Chae

    IPC分类号： H01L45/00 ,  H01L27/24

    CPC分类号： H01L45/1253 ,  H01L27/2472 ,  H01L27/249 ,  H01L45/04 ,  H01L45/1226 ,  H01L45/146

    摘要： A nonvolatile memory cell includes first and second interlayer insulating films which are separated from each other and are stacked sequentially, a first electrode which penetrates the first interlayer insulating film and the second interlayer insulating film, a resistance change film which is formed along a side surface of the first electrode and extends parallel to the first electrode, and a second electrode which is formed between the first interlayer insulating film and the second interlayer insulating film. The second electrode includes a conductive film which is made of metal and a diffusion preventing film which prevents diffusion of a conductive material contained in the conductive film.

    摘要翻译： 非易失性存储单元包括彼此分离并依次堆叠的第一和第二层间绝缘膜，穿过第一层间绝缘膜和第二层间绝缘膜的第一电极，沿着侧表面形成的电阻变化膜 并且平行于第一电极延伸，以及形成在第一层间绝缘膜和第二层间绝缘膜之间的第二电极。 第二电极包括由金属制成的导电膜和防止导电膜中包含的导电材料扩散的防扩散膜。