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373 条记录 (耗时 0.036 秒)

    Adhesive composition for use in packaging applications
    1.
    发明授权
    Adhesive composition for use in packaging applications 失效

    公开(公告)号：US06339259B1

    公开(公告)日：2002-01-15

    申请号：US09065944

    申请日：1998-04-24

    申请人： Chad A. Cobbley ,  Tongbi Jiang ,  Edward A. Schrock

    发明人： Chad A. Cobbley ,  Tongbi Jiang ,  Edward A. Schrock

    IPC分类号： H01L2348

    摘要： An adhesive composition and methods incorporating the adhesive composition in semiconductor applications are provided. The adhesive composition is an instant setting adhesive composition that does not require external energy input such as heat or radiation such for application of the adhesive composition on a surface. The instant setting composition possesses sufficient thixotropic characteristics such that applying the instant setting adhesive composition to a surface can be accomplished by a variety of application techniques and in a variety of patterns. Once applied to the surface, the instant setting adhesive composition sets to retain the discrete pattern as applied, in a relatively short period of time, typically from about 0.10 to about 120 seconds at an ambient temperature, typically from 20° C. to 30° C. Advantageously, the instant setting adhesive composition can be screen printed on a semiconductor wafer prior to singulation because streets between the dice are essentially free of the instant setting adhesive composition.

    Apparatus for improving stencil/screen print quality
    5.
    发明授权
    Apparatus for improving stencil/screen print quality 失效
    提高模板/丝网印刷质量的设备

    公开(公告)号：US07476277B2

    公开(公告)日：2009-01-13

    申请号：US10701140

    申请日：2003-11-04

    申请人： Tongbi Jiang ,  Chad A. Cobbley ,  John VanNortwick

    发明人： Tongbi Jiang ,  Chad A. Cobbley ,  John VanNortwick

    IPC分类号： B05C11/00

    CPC分类号： B41C1/14 ,  B41N1/242 ,  H01L2224/4826 ,  H05K3/1225 ,  Y10S438/945

    摘要： A method and apparatus for improved stencil/screen print quality is disclosed. The stencil or screen assists in application of a printable material onto a substrate, such as an adhesive to a semiconductor die of a semiconductor wafer during a lead-on-chip (LOC) packaging process. In one embodiment, the stencil includes a coating applied to at least one surface of a pattern of the stencil or screen to retard running of the printable material onto the surface. In another embodiment, the stencil or screen includes a second coating applied to at least one other surface of the pattern to promote spreading of the printable material onto the substrate.

    摘要翻译： 公开了一种用于改进模板/丝网印刷质量的方法和装置。 在片上（LOC）包装过程中，模板或屏幕有助于将可印刷材料施加到基底上，例如对半导体晶片的半导体管芯的粘合剂。 在一个实施例中，模板包括施加到模板或筛网的图案的至少一个表面上的涂层，以阻止可印刷材料运动到表面上。 在另一个实施例中，模板或丝网包括施加到图案的至少一个其他表面的第二涂层，以促进可印刷材料在基底上的铺展。

    Method for in-line testing of flip-chip semiconductor assemblies
    6.
    发明授权
    Method for in-line testing of flip-chip semiconductor assemblies 失效

    公开(公告)号：US07105366B2

    公开(公告)日：2006-09-12

    申请号：US10338522

    申请日：2005-09-08

    申请人： Chad A. Cobbley ,  John VanNortwick ,  Bret K. Street ,  Tongbi Jiang

    发明人： Chad A. Cobbley ,  John VanNortwick ,  Bret K. Street ,  Tongbi Jiang

    IPC分类号： G01R31/26

    CPC分类号： G01R1/0483 ,  Y10T29/4913 ,  Y10T29/49144

    摘要： Flip-chip semiconductor assemblies, each including integrated circuit (IC) dice and an associated substrate, are electrically tested before encapsulation using an in-line or in situ test socket or probes at a die-attach station. Those assemblies using “wet” quick-cure epoxies for die attachment may be tested prior to the epoxy being cured by pressing the integrated circuit (IC) dice against interconnection points on the substrate for electrical connection, while those assemblies using “dry” epoxies may be cured prior to testing. In either case, any failures in the dice or in the interconnections between the dice and the substrates can be easily fixed, and the need for the use of known-good-die (KGD) rework procedures during repair is eliminated.

    Method for in-line testing of flip-chip semiconductor assemblies
    7.
    发明授权
    Method for in-line testing of flip-chip semiconductor assemblies 失效

    公开(公告)号：US07005878B2

    公开(公告)日：2006-02-28

    申请号：US10900610

    申请日：2004-07-27

    申请人： Chad A. Cobbley ,  John VanNortwick ,  Bret K. Street ,  Tongbi Jiang

    发明人： Chad A. Cobbley ,  John VanNortwick ,  Bret K. Street ,  Tongbi Jiang

    IPC分类号： G01R31/26

    CPC分类号： G01R1/0483 ,  Y10T29/4913 ,  Y10T29/49144

    摘要： Flip-chip semiconductor assemblies, each including integrated circuit (IC) dice and an associated substrate, are electrically tested before encapsulation using an in-line or in situ test socket or probes at a die-attach station. Those assemblies using “wet” quick-cure epoxies for die attachment may be tested prior to the epoxy being cured by pressing the integrated circuit (IC) dice against interconnection points on the substrate for electrical connection, while those assemblies using “dry” epoxies may be cured prior to testing. In either case, any failures in the dice or in the interconnections between the dice and the substrates can be easily fixed, and the need for the use of known-good-die (KGD) rework procedures during repair is eliminated.

    Method for in-line testing of flip-chip semiconductor assemblies
    8.
    发明授权
    Method for in-line testing of flip-chip semiconductor assemblies 失效
    倒装芯片半导体组件的在线测试方法

    公开(公告)号：US06369602B1

    公开(公告)日：2002-04-09

    申请号：US09645902

    申请日：2000-08-25

    申请人： Chad A. Cobbley ,  John VanNortwick ,  Bret K. Street ,  Tongbi Jiang

    发明人： Chad A. Cobbley ,  John VanNortwick ,  Bret K. Street ,  Tongbi Jiang

    IPC分类号： G01R3126

    CPC分类号： G01R1/0483 ,  Y10T29/4913 ,  Y10T29/49144

    摘要： Flip-chip semiconductor assemblies, each including integrated circuit (IC) dice and an associated substrate, are electrically tested before encapsulation using an in-line or in-situ test socket or probes at a die-attach station. Those assemblies using “wet” quick-cure epoxies for die-attachment may be tested prior to the epoxy being cured by pressing the integrated circuit (IC) dice against interconnection points on the substrate for electrical connection, while those assemblies using “dry” epoxies may be cured prior to testing. In either case, any failures in the dice or in the interconnections between the dice and the substrates can be easily fixed, and the need for the use of known-good-die (KGD) rework procedures during repair is eliminated.

    摘要翻译： 每个包括集成电路（IC）裸片和相关衬底的倒装芯片半导体组件在封装之前使用在线或原位测试插座或芯片附接站的探针进行电测试。 在通过将集成电路（IC）芯片压在基板上的互连点进行电连接而使环氧树脂固化之前，可以测试使用“湿”快速固化环氧树脂进行芯片附着的那些组件，而使用“干”环氧树脂 可以在测试之前治愈。 在任一种情况下，骰子或骰子与基板之间的互连中的任何故障都可以很容易地固定，并且消除了在维修期间使用已知好模具（KGD）返工程序的需要。