公开(公告)号：US06566650B1

公开(公告)日：2003-05-20

申请号：US09664418

申请日：2000-09-18

申请人： Chang Chaun Hu ,  Kin Leong Pey ,  Yung Fu Chong ,  Chim Wai Kin ,  Pavel Neuzil ,  Lap Chan

发明人： Chang Chaun Hu ,  Kin Leong Pey ,  Yung Fu Chong ,  Chim Wai Kin ,  Pavel Neuzil ,  Lap Chan

IPC分类号： B01D5944

CPC分类号： G01Q60/58 ,  Y10S977/867 ,  Y10S977/875

摘要： One of the limitations to current usage of scanning thermal microscopes arises when one needs to obtain a thermal map of an electrically biased specimen. Current practice is for the conductive parts of the specimen to be passivated to prevent excessive current leakage between the tip and the conductive sample. The present invention eliminates the need for this by coating the probe's microtip with a layer of insulation that is also a good thermal conductor. Examples of both thermocouple and thermistor based probes are given along with processes for their manufacture.

摘要翻译： 当需要获得电偏置样本的热图时，会出现当前使用扫描热显微镜的局限性。 目前的做法是使样品的导电部件被钝化，以防止尖端和导电样品之间的过大的电流泄漏。 本发明通过用也是良好热导体的绝缘层涂覆探针的微尖头来消除对此的需要。 给出了热电偶和基于热敏电阻的探针的实例以及其制造方法。

公开(公告)号：US20100124809A1

公开(公告)日：2010-05-20

申请号：US12271262

申请日：2008-11-14

申请人： Kuang Kian Ong ,  Sai Hooi Yeong ,  Kin Leong Pey ,  Lap Chan ,  Yung Fu Chong

发明人： Kuang Kian Ong ,  Sai Hooi Yeong ,  Kin Leong Pey ,  Lap Chan ,  Yung Fu Chong

IPC分类号： H01L21/336 ,  H01L21/265

CPC分类号： H01L21/26506 ,  H01L21/26513 ,  H01L21/268 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659

摘要： A method for forming a shallow junction region in a crystalline semiconductor substrate and method for fabricating a semiconductor device having the shallow junction region includes a defect engineering step in which first ions are introduced into a first region of the substrate and vacancies are generated in the first region. During the generation of substrate vacancies, the first region remains substantially crystalline. Interstitial species are generated in a second region and second ions are introduced into the second region to capture the interstitial species. Laser annealing is used to activate dopant species in the first region and repair implantation damage in the second region. The defect engineering process creates a vacancy-rich surface region in which source and drain extension regions having high dopant activation and low sheet resistance are created in an MOS device.

摘要翻译： 在结晶半导体衬底中形成浅结区域的方法和具有浅结区域的半导体器件的制造方法包括缺陷工程步骤，其中将第一离子引入到衬底的第一区域中，并且在第一衬底中产生空位 地区。 在产生衬底空位期间，第一区域保持基本上结晶。 在第二区域中产生间质物质，并且将第二离子引入第二区域以捕获间质物质。 激光退火用于激活第一区域中的掺杂物质并修复第二区域中的植入损伤。 缺陷工程过程产生空位丰富的表面区域，其中在MOS器件中产生具有高掺杂剂激活和低薄层电阻的源极和漏极延伸区域。

公开(公告)号：US06387784B1

公开(公告)日：2002-05-14

申请号：US09810121

申请日：2001-03-19

申请人： Yung Fu Chong ,  Randall Cher Liang Cha ,  Lap Chan ,  Kin Leong Pey

发明人： Yung Fu Chong ,  Randall Cher Liang Cha ,  Lap Chan ,  Kin Leong Pey

IPC分类号： H01L214763

CPC分类号： H01L29/6656 ,  H01L21/76886

摘要： A method is provided to reduce poly depletion in MOS transistors. Conventionally, after a polysilicon electrode has been doped, an anneal step is usually performed to activate the dopants. However, the anneal step may be insufficient to drive the implanted impurities down the entire depth of the polysilicon electrode. Consequently, a portion of the polysilicon gate nearest to the gate oxide will be depleted of dopants. This poly depletion will have a detrimental effect on the control of the threshold voltage, and hence on the performance of the device. It is disclosed in the present invention a method of forming polysilicon gates where dopant depletion at the interface near the gate oxide layer is alleviated substantially by using laser annealing; however, by first pre-amorphizing the polycrystalline silicon prior to ion (implantation to a desired depth such that during laser annealing the dopants will diffuse uniformly to a melt depth. In this manner, poly depletion effect is greatly reduced and hence performance of the device improved. The disclosed method is applicable to both n+ doped polysilicon gates (NMOS) and p+ doped polysilicon gates (PMOS).

摘要翻译： 提供了一种减少MOS晶体管多余耗尽的方法。 通常，在掺杂多晶硅电极之后，通常进行退火步骤以激活掺杂剂。 然而，退火步骤可能不足以在多晶硅电极的整个深度下驱动注入的杂质。 因此，最接近栅极氧化物的多晶硅栅极的一部分将耗尽掺杂剂。 这种多余耗尽将对阈值电压的控制以及因此对器件的性能具有不利影响。 在本发明中公开了一种形成多晶硅栅极的方法，其中在栅极氧化物层附近的界面处的掺杂剂消耗基本上通过使用激光退火得到缓解; 然而，通过在离子之前首先将多晶硅预先失配（植入到期望的深度，使得在激光退火期间，掺杂剂将均匀地扩散到熔体深度），以这种方式，多余的效应被大大降低，因此器件的性能 所公开的方法适用于n +掺杂多晶硅栅极（NMOS）和p +掺杂多晶硅栅极（PMOS）。

公开(公告)号：US07888224B2

公开(公告)日：2011-02-15

申请号：US12271262

申请日：2008-11-14

申请人： Kuang Kian Ong ,  Sai Hooi Yeong ,  Kin Leong Pey ,  Lap Chan ,  Yung Fu Chong

发明人： Kuang Kian Ong ,  Sai Hooi Yeong ,  Kin Leong Pey ,  Lap Chan ,  Yung Fu Chong

IPC分类号： H01L21/336

CPC分类号： H01L21/26506 ,  H01L21/26513 ,  H01L21/268 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659

摘要： A method for forming a shallow junction region in a crystalline semiconductor substrate and method for fabricating a semiconductor device having the shallow junction region includes a defect engineering step in which first ions are introduced into a first region of the substrate and vacancies are generated in the first region. During the generation of substrate vacancies, the first region remains substantially crystalline. Interstitial species are generated in a second region and second ions are introduced into the second region to capture the interstitial species. Laser annealing is used to activate dopant species in the first region and repair implantation damage in the second region. The defect engineering process creates a vacancy-rich surface region in which source and drain extension regions having high dopant activation and low sheet resistance are created in an MOS device.

摘要翻译： 一种在晶体半导体衬底中形成浅结区的方法和用于制造具有浅结区的半导体器件的方法包括：缺陷工程步骤，其中将第一离子引入衬底的第一区域，并且在第一衬底中产生空位 地区。 在产生衬底空位期间，第一区域保持基本上结晶。 在第二区域中产生间质物质，并且将第二离子引入第二区域以捕获间质物质。 激光退火用于激活第一区域中的掺杂物质并修复第二区域中的植入损伤。 缺陷工程过程产生空位丰富的表面区域，其中在MOS器件中产生具有高掺杂剂激活和低薄层电阻的源极和漏极延伸区域。

公开(公告)号：US07892905B2

公开(公告)日：2011-02-22

申请号：US11195196

申请日：2005-08-02

申请人： Kuang Kian Ong ,  Kin Leong Pey ,  King Jien Chui ,  Ganesh Samudra ,  Yee Chia Yeo ,  Yung Fu Chong

发明人： Kuang Kian Ong ,  Kin Leong Pey ,  King Jien Chui ,  Ganesh Samudra ,  Yee Chia Yeo ,  Yung Fu Chong

IPC分类号： H01L31/0216 ,  H01L21/336

CPC分类号： H01L29/7848 ,  H01L21/02532 ,  H01L21/02675 ,  H01L21/268 ,  H01L21/7624 ,  H01L29/165 ,  H01L29/665 ,  H01L29/66628 ,  Y10S438/938

摘要： A process for forming a strained channel region for a MOSFET device via formation of adjacent silicon-germanium source/drain regions, has been developed. The process features either blanket deposition of a silicon-germanium layer, or selective growth of a silicon-germanium layer on exposed portions of a source/drain extension region. A laser anneal procedure results in formation of a silicon-germanium source/drain region via consumption of a bottom portion of the silicon-germanium layer and a top portion of the underlying source/drain region. Optimization of the formation of the silicon-germanium source/drain region via laser annealing can be achieved via a pre-amorphization implantation (PAI) procedure applied to exposed portions of the source/drain region prior to deposition of the silicon-germanium layer. Un-reacted top portions of the silicon-germanium layer are selectively removed after the laser anneal procedure.

摘要翻译： 已经开发了通过形成相邻的硅 - 锗源/漏区来形成用于MOSFET器件的应变沟道区的工艺。 该方法的特征在于硅 - 锗层的覆盖沉积，或硅 - 锗层在源极/漏极延伸区域的暴露部分上的选择性生长。 激光退火程序通过消耗硅 - 锗层的底部部分和下面的源极/漏极区域的顶部部分而导致硅 - 锗源极/漏极区域的形成。 通过经由激光退火形成硅 - 锗源/漏区的优化可以通过在沉积硅 - 锗层之前施加到源/漏区的暴露部分的预非晶化注入（PAI）程序来实现。 在激光退火过程之后，硅 - 锗层的未反应顶部被选择性地去除。

公开(公告)号：US06391731B1

公开(公告)日：2002-05-21

申请号：US09784251

申请日：2001-02-15

申请人： Yung Fu Chong ,  Kin Leong Pey ,  Alex See

发明人： Yung Fu Chong ,  Kin Leong Pey ,  Alex See

IPC分类号： H01L21336

CPC分类号： H01L21/26513 ,  H01L21/26506 ,  H01L21/268 ,  H01L21/324 ,  H01L29/6653 ,  H01L29/6659

摘要： A new method of forming MOS transistors with shallow source and drain extensions and deep source and drain junctions in the manufacture of an integrated circuit device has been achieved. Gates are provided overlying a semiconductor substrate. Temporary sidewall spacers are formed on the gates. Ions are implanted into the exposed semiconductor substrate to form a deep amorphous layer. Ions are implanted into the deep amorphous layer to form pre-annealed source and drain junctions. The temporary sidewall spacers are removed. Ions are implanted into the exposed semiconductor substrate to form a shallow amorphous layer. Ions are implanted into the shallow amorphous layer to form pre-annealed source and drain extensions. A capping layer may be deposited overlying the semiconductor substrate and the gates to protect the semiconductor substrate during irradiation. The semiconductor substrate is irradiated with laser light to melt the amorphous layer while the crystalline regions of the semiconductor substrate remain in solid state. Ions in the pre-annealed source and drain junctions diffuse in the deep amorphous layer while ions in the pre-annealed source and drain extensions diffuse into the shallower amorphous layer. The source and drain junctions and the source and drain extensions for the transistors are thereby simultaneously formed.

摘要翻译： 已经实现了在集成电路器件的制造中形成具有浅源极和漏极延伸以及深源极和漏极结的MOS晶体管的新方法。 盖板覆盖半导体衬底。 在门上形成临时侧墙。 将离子注入到暴露的半导体衬底中以形成深非晶层。 将离子注入到深非晶层中以形成预退火的源极和漏极结。 移除临时侧壁间隔物。 将离子注入到暴露的半导体衬底中以形成浅的非晶层。 将离子注入到浅非晶层中以形成预退火的源极和漏极延伸。 覆盖半导体衬底和栅极的覆盖层可以沉积，以在照射期间保护半导体衬底。 半导体衬底用激光照射以熔化非晶层，同时半导体衬底的结晶区保持固态。 预退火源极和漏极结中的离子在深非晶层中扩散，而预退火的源极和漏极延伸部中的离子扩散到较浅的非晶层中。 从而同时形成晶体管的源极和漏极结以及源极和漏极延伸。

公开(公告)号：US06365446B1

公开(公告)日：2002-04-02

申请号：US09609751

申请日：2000-07-03

申请人： Yung Fu Chong ,  Kin Leong Pey ,  Alex See

发明人： Yung Fu Chong ,  Kin Leong Pey ,  Alex See

IPC分类号： H01L21336

CPC分类号： H01L21/28518 ,  H01L21/26506 ,  H01L21/2652 ,  H01L21/268 ,  H01L21/28052 ,  H01L29/665

摘要： A method for producing MOS type transistors with deep source/drain junctions and thin, silicided contacts with desireable interfacial and electrical properties. The devices are produced by a method that involves pre-amorphization of the gate, source and drain regions by ion-implantation, the formation of a metal layer, ion implantation through the metal layer, the formation of a capping layer and a subsequent laser anneal.

摘要翻译： 一种用于制造具有深源极/漏极结的MOS型晶体管和具有期望的界面和电学性质的薄的硅化物触点的方法。 这些器件通过一种方法产生，该方法涉及通过离子注入，栅极，源极和漏极区域的非晶化，金属层的形成，通过金属层的离子注入，形成覆盖层和随后的激光退火 。

公开(公告)号：US06335253B1

公开(公告)日：2002-01-01

申请号：US09614557

申请日：2000-07-12

申请人： Yung Fu Chong ,  Kin Leong Pey ,  Alex See ,  Andrew Thye Shen Wee

发明人： Yung Fu Chong ,  Kin Leong Pey ,  Alex See ,  Andrew Thye Shen Wee

IPC分类号： H01L21336

CPC分类号： H01L21/268 ,  H01L21/26513 ,  H01L21/324 ,  H01L29/665 ,  H01L29/6659

摘要： A new method of forming MOS transistors with shallow source and drain extensions and self-aligned silicide in the has been achieved. Gates are provided overlying a semiconductor substrate. Temporary sidewall spacers are formed on the gates. Ions are implanted into the semiconductor substrate and the polysilicon layer to form deep amorphous layers beside the spacers and shallow amorphous layers under the spacers. The spacers are removed. Ions are implanted to form lightly doped junctions in the shallower amorphous layer. Permanent sidewall spacers are formed on the gates. Ions are implanted to form heavily doped junctions in the deeper amorphous layer. A metal layer is deposited. A capping layer is deposited to protect the metal layer during irradiation. The integrated circuit device is irradiated with laser light to melt the amorphous layer while the crystalline polysilicon and semiconductor substrate remain in solid state. The metal layer is heated, and may be melted, to cause reaction with the silicon to form silicide. Ions in the heavily doped junctions and in the lightly doped junctions are also thereby diffused into the amorphous layer. The deep source and drain junctions, the shallow source and drain extensions, and a silicide layer are simultaneously formed. A heat treatment crystallizes the silicide to improve resistivity.

摘要翻译： 已经实现了一种形成具有浅源极和漏极延伸和自对准硅化物的MOS晶体管的新方法。 盖板覆盖半导体衬底。 在门上形成临时侧墙。 将离子注入到半导体衬底和多晶硅层中，以在间隔物旁边的隔离层和浅非晶层之间形成深非晶层。 去除间隔物。 在较浅的非晶层中植入离子以形成轻掺杂的结。 在门上形成永久侧壁间隔物。 植入离子以在较深的非晶层中形成重掺杂的结。 沉积金属层。 沉积覆盖层以在照射期间保护金属层。 用激光照射集成电路器件以熔化非晶层，同时晶体多晶硅和半导体衬底保持固态。 金属层被加热并且可能被熔化，从而与硅反应形成硅化物。 在重掺杂结和轻掺杂结中的离子也因此扩散到非晶层中。 同时形成深源极和漏极结，浅源极和漏极延伸部分以及硅化物层。 热处理使硅化物结晶以提高电阻率。

公开(公告)号：US06624489B2

公开(公告)日：2003-09-23

申请号：US10033284

申请日：2001-12-31

申请人： Yung Fu Chong ,  Kin Leong Pey ,  Alex See

发明人： Yung Fu Chong ,  Kin Leong Pey ,  Alex See

IPC分类号： H01L2976

CPC分类号： H01L21/28518 ,  H01L21/26506 ,  H01L21/2652 ,  H01L21/268 ,  H01L21/28052 ,  H01L29/665

摘要： A method for producing MOS type transistors with deep source/drain junctions and thin, silicided contacts with desireable interfacial and electrical properties. The devices are produced by a method that involves pre-amorphization of the gate, source and drain regions by ion-implantation, the formation of a metal layer, ion implantation through the metal layer, the formation of a capping layer and a subsequent laser anneal.

公开(公告)号：US06534390B1

公开(公告)日：2003-03-18

申请号：US10050444

申请日：2002-01-16

申请人： Yung Fu Chong ,  Randall Cha ,  Kin Leong Pey

发明人： Yung Fu Chong ,  Randall Cha ,  Kin Leong Pey

IPC分类号： H01L213205

CPC分类号： H01L29/665 ,  H01L21/28052 ,  H01L21/28518 ,  H01L21/3212 ,  H01L29/41783 ,  H01L29/66545

摘要： The present invention provides an improved semiconductor device of a Silicon/Amorphous Silicon/Metal Structure (SASM) and a method of making an improved semiconductor device by a salicide process by using an anneal to form a thick silicide film on shallow source/drain regions and a chemical-mechanical polish (CMP) step is then performed to remove the silicide over the top of the spacers at the gate, thus breaking the continuity of the silicide film extending from the gate to the source drain region.

摘要翻译： 本发明提供一种硅/非晶硅/金属结构（SASM）的改进的半导体器件以及通过使用退火在硅源/漏区上形成厚硅化物膜而通过自对准硅化物工艺制造改进的半导体器件的方法， 然后执行化学机械抛光（CMP）步骤以在栅极处去除间隔物的顶部上的硅化物，从而破坏从栅极延伸到源极漏极区的硅化物膜的连续性。