公开(公告)号：US08570805B2

公开(公告)日：2013-10-29

申请号：US13029518

申请日：2011-02-17

申请人： Changhyun Lee ,  Jinman Han ,  Doogon Kim ,  Sunghoi Hur ,  Jongin Yun

发明人： Changhyun Lee ,  Jinman Han ,  Doogon Kim ,  Sunghoi Hur ,  Jongin Yun

IPC分类号： G11C16/04

CPC分类号： G11C16/107 ,  G11C16/0483 ,  G11C16/10 ,  G11C2213/71 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/7926

摘要： Provided is a programming method of a nonvolatile memory device. The nonvolatile memory device includes a substrate and a plurality of memory cells which are stacked in the direction perpendicular to the substrate. The programming method applies a first voltage to a selected bit line connected to at least two memory strings in same column including a memory cell of the plurality of memory cell to be programmed, applies a second voltage to an unselected bit line connected to at least two memory strings in same column including a memory cell of the plurality of memory cell to be program-prohibited, applies a third voltage to a selected string selection line connected to at least two memory strings in same row, applies a fourth voltage to an unselected string selection line connected to at least two memory strings in same row, and applies a program operation voltage to a plurality of word lines, each word line connected to each corresponding memory cell in the memory string, wherein the first to third voltages are positive voltages.

公开(公告)号：US20110199829A1

公开(公告)日：2011-08-18

申请号：US13029518

申请日：2011-02-17

申请人： Changhyun Lee ,  Jinman Han ,  Doogon Kim ,  Sunghoi Hur ,  Jongin Yun

发明人： Changhyun Lee ,  Jinman Han ,  Doogon Kim ,  Sunghoi Hur ,  Jongin Yun

IPC分类号： G11C16/04 ,  G11C16/10

CPC分类号： G11C16/107 ,  G11C16/0483 ,  G11C16/10 ,  G11C2213/71 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/7926

摘要： Provided is a programming method of a nonvolatile memory device. The nonvolatile memory device includes a substrate and a plurality of memory cells which are stacked in the direction perpendicular to the substrate. The programming method applies a first voltage to a selected bit line connected to at least two memory strings in same column including a memory cell of the plurality of memory cell to be programmed, applies a second voltage to an unselected bit line connected to at least two memory strings in same column including a memory cell of the plurality of memory cell to be program-prohibited, applies a third voltage to a selected string selection line connected to at least two memory strings in same row, applies a fourth voltage to an unselected string selection line connected to at least two memory strings in same row, and applies a program operation voltage to a plurality of word lines, each word line connected to each corresponding memory cell in the memory string, wherein the first to third voltages are positive voltages.

摘要翻译： 提供了一种非易失性存储器件的编程方法。 非易失性存储器件包括基板和沿垂直于基板的方向堆叠的多个存储单元。 编程方法将第一电压施加到连接到包括要编程的多个存储器单元的存储单元的同一列中的至少两个存储器串的选定位线，将第二电压施加到连接至少两个的未选定位线 包含要被编程禁止的多个存储单元的存储单元的同一列中的存储器串向同一行中连接到至少两个存储器串的所选择的串选择线施加第三电压，将第四电压施加到未选择的串 选择线连接到同一行中的至少两个存储器串，并且将编程操作电压施加到多个字线，每个字线连接到存储器串中的每个对应的存储单元，其中第一至第三电压是正电压。

公开(公告)号：US08929145B2

公开(公告)日：2015-01-06

申请号：US14043256

申请日：2013-10-01

申请人： Changhyun Lee ,  Jinman Han ,  Doogon Kim ,  Sunghoi Hur ,  Jongin Yun

发明人： Changhyun Lee ,  Jinman Han ,  Doogon Kim ,  Sunghoi Hur ,  Jongin Yun

IPC分类号： G11C16/04 ,  H01L27/115 ,  G11C16/10 ,  H01L29/792

CPC分类号： G11C16/107 ,  G11C16/0483 ,  G11C16/10 ,  G11C2213/71 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/7926

摘要： Provided is a programming method of a nonvolatile memory device. The nonvolatile memory device includes a substrate and a plurality of memory cells which are stacked in the direction perpendicular to the substrate. The programming method applies a first voltage to a selected bit line connected to at least two memory strings in same column including a memory cell of the plurality of memory cell to be programmed, applies a second voltage to an unselected bit line connected to at least two memory strings in same column including a memory cell of the plurality of memory cell to be program-prohibited, applies a third voltage to a selected string selection line connected to at least two memory strings in same row, applies a fourth voltage to an unselected string selection line connected to at least two memory strings in same row, and applies a program operation voltage to a plurality of word lines, each word line connected to each corresponding memory cell in the memory string, wherein the first to third voltages are positive voltages.

摘要翻译： 提供了一种非易失性存储器件的编程方法。 非易失性存储器件包括基板和沿垂直于基板的方向堆叠的多个存储单元。 编程方法将第一电压施加到连接到包括要编程的多个存储器单元的存储单元的同一列中的至少两个存储器串的选定位线，将第二电压施加到连接至少两个的未选定位线 包含要被编程禁止的多个存储单元的存储单元的同一列中的存储器串向同一行中连接到至少两个存储器串的所选择的串选择线施加第三电压，将第四电压施加到未选择的串 选择线连接到同一行中的至少两个存储器串，并且将编程操作电压施加到多个字线，每个字线连接到存储器串中的每个对应的存储单元，其中第一至第三电压是正电压。

公开(公告)号：US08848456B2

公开(公告)日：2014-09-30

申请号：US13967455

申请日：2013-08-15

申请人： Jinman Han ,  Doogon Kim

发明人： Jinman Han ,  Doogon Kim

IPC分类号： G11C11/34 ,  G11C16/16 ,  G11C16/08 ,  G11C16/14 ,  G11C16/04

CPC分类号： G11C16/14 ,  G11C16/04 ,  G11C16/08 ,  G11C16/16 ,  H01L27/1157 ,  H01L27/11582

摘要： Provided is an erasing method of a nonvolatile memory device. The erasing method applies a word line erase voltage to a plurality of word lines connected to the memory cells respectively, applies a specific voltage to a ground selection line connected to the ground selection transistor, applies an erase voltage to a substrate in which the memory string formed during the step applying the specific voltage to the ground selection line, and floats the ground selection line in response to a voltage change of the substrate.

摘要翻译： 提供了一种非易失性存储器件的擦除方法。 擦除方法将字线擦除电压分别施加到连接到存储器单元的多个字线，向连接到接地选择晶体管的接地选择线施加特定电压，将擦除电压施加到其中存储器串 在施加特定电压到地选择线的步骤期间形成，并且响应于衬底的电压变化漂浮地选择线。

公开(公告)号：US20120275234A1

公开(公告)日：2012-11-01

申请号：US13545588

申请日：2012-07-10

申请人： Ho-Chul Lee ,  Doogon Kim ,  Jinman Han

发明人： Ho-Chul Lee ,  Doogon Kim ,  Jinman Han

IPC分类号： G11C16/06

CPC分类号： G11C16/16 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/14

摘要： A nonvolatile memory device configured to apply a wordline erase voltage to a plurality of wordlines connected to a plurality of memory cells, apply an erase voltage to a substrate where a memory cell string is formed while applying a specific voltage to at least one ground selection line connected to at least one ground selection transistor, and float the at least one ground selection line when a target voltage of the substrate reaches a target voltage.

摘要翻译： 非易失性存储器件被配置为向连接到多个存储器单元的多个字线施加字线擦除电压，将擦除电压施加到形成存储单元串的衬底上，同时向至少一个接地选择线施加特定电压 连接到至少一个接地选择晶体管，并且当所述衬底的目标电压达到目标电压时浮置所述至少一个接地选择线。

公开(公告)号：US08792282B2

公开(公告)日：2014-07-29

申请号：US13545588

申请日：2012-07-10

申请人： Ho-Chul Lee ,  Doogon Kim ,  Jinman Han

发明人： Ho-Chul Lee ,  Doogon Kim ,  Jinman Han

IPC分类号： G11C11/34 ,  G11C16/16 ,  G11C16/14 ,  G11C16/04

CPC分类号： G11C16/16 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/14

摘要： A nonvolatile memory device configured to apply a wordline erase voltage to a plurality of wordlines connected to a plurality of memory cells, apply an erase voltage to a substrate where a memory cell string is formed while applying a specific voltage to at least one ground selection line connected to at least one ground selection transistor, and float the at least one ground selection line when a target voltage of the substrate reaches a target voltage.

摘要翻译： 非易失性存储器件被配置为向连接到多个存储器单元的多个字线施加字线擦除电压，将擦除电压施加到形成存储单元串的衬底上，同时向至少一个接地选择线施加特定电压 连接到至少一个接地选择晶体管，并且当所述衬底的目标电压达到目标电压时浮置所述至少一个接地选择线。

公开(公告)号：US08553466B2

公开(公告)日：2013-10-08

申请号：US13023934

申请日：2011-02-09

申请人： Jinman Han ,  Doogon Kim

发明人： Jinman Han ,  Doogon Kim

IPC分类号： G11C11/34

CPC分类号： G11C16/14 ,  G11C16/04 ,  G11C16/08 ,  G11C16/16 ,  H01L27/1157 ,  H01L27/11582

摘要： Provided is an erasing method of a nonvolatile memory device. The erasing method applies a word line erase voltage to a plurality of word lines connected to the memory cells respectively, applies a specific voltage to a ground selection line connected to the ground selection transistor, applies an erase voltage to a substrate in which the memory string formed during the step applying the specific voltage to the ground selection line, and floats the ground selection line in response to a voltage change of the substrate.

摘要翻译： 提供了一种非易失性存储器件的擦除方法。 擦除方法将字线擦除电压分别施加到连接到存储器单元的多个字线，向连接到接地选择晶体管的接地选择线施加特定电压，将擦除电压施加到其中存储器串 在施加特定电压到地选择线的步骤期间形成，并且响应于衬底的电压变化漂浮地选择线。

公开(公告)号：US20110216603A1

公开(公告)日：2011-09-08

申请号：US13023934

申请日：2011-02-09

申请人： Jinman Han ,  Doogon Kim

发明人： Jinman Han ,  Doogon Kim

IPC分类号： G11C16/08 ,  G11C16/04 ,  G11C16/16

CPC分类号： G11C16/14 ,  G11C16/04 ,  G11C16/08 ,  G11C16/16 ,  H01L27/1157 ,  H01L27/11582

摘要： Provided is an erasing method of a nonvolatile memory device. The erasing method applies a word line erase voltage to a plurality of word lines connected to the memory cells respectively, applies a specific voltage to a ground selection line connected to the ground selection transistor, applies an erase voltage to a substrate in which the memory string formed during the step applying the specific voltage to the ground selection line, and floats the ground selection line in response to a voltage change of the substrate.

摘要翻译： 提供了一种非易失性存储器件的擦除方法。 擦除方法将字线擦除电压分别施加到连接到存储器单元的多个字线，向连接到接地选择晶体管的接地选择线施加特定电压，将擦除电压施加到其中存储器串 在施加特定电压到地选择线的步骤期间形成，并且响应于衬底的电压变化漂浮地选择线。

公开(公告)号：US09378831B2

公开(公告)日：2016-06-28

申请号：US14820895

申请日：2015-08-07

申请人： Jinman Han ,  Sun-Il Shim ,  Donghyuk Chae ,  Jae-Hoon Jang ,  Youngho Lim ,  Hansoo Kim ,  Jaehun Jeong

发明人： Jinman Han ,  Sun-Il Shim ,  Donghyuk Chae ,  Jae-Hoon Jang ,  Youngho Lim ,  Hansoo Kim ,  Jaehun Jeong

IPC分类号： G11C16/04 ,  G11C16/14 ,  G11C16/16 ,  G11C16/08 ,  G11C16/12 ,  G11C16/26 ,  G11C16/34 ,  H01L27/115

CPC分类号： G11C16/14 ,  G11C16/0466 ,  G11C16/0475 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/12 ,  G11C16/16 ,  G11C16/26 ,  G11C16/3418 ,  H01L27/1157 ,  H01L27/11582

摘要： Nonvolatile memory device, operating methods thereof, and memory systems including the same. In the operating method, a ground select line of a first string connected to a bit line may be floated. An erase prohibition voltage may be applied to a ground select line of a second string connected to the bit line. An erase operation voltage may be applied to the first and second strings.

摘要翻译： 非易失性存储器件，其操作方法和包括该非易失性存储器件的存储器系统。 在操作方法中，连接到位线的第一串的接地选择线可以浮置。 可以将擦除禁止电压施加到连接到位线的第二串的接地选择线。 可以将擦除操作电压施加到第一和第二串。

公开(公告)号：US09324440B2

公开(公告)日：2016-04-26

申请号：US14631341

申请日：2015-02-25

申请人： Sang-Won Park ,  Dongku Kang ,  Jung-Yun Yun ,  Jinman Han ,  ChiWeon Yoon

发明人： Sang-Won Park ,  Dongku Kang ,  Jung-Yun Yun ,  Jinman Han ,  ChiWeon Yoon

IPC分类号： G11C16/16 ,  G11C16/14 ,  G11C16/04 ,  G11C16/34

CPC分类号： G11C16/14 ,  G11C16/0483 ,  G11C16/16 ,  G11C16/3445 ,  H01L27/11582

摘要： The inventive concept relates to a nonvolatile memory device and methods for operating the same. The nonvolatile memory device comprises a plurality of strings arranged in rows and columns on a substrate, each string including at least one ground select transistor, a plurality of memory cells and at least one string select transistor sequentially stacked on the substrate. The method comprises erasing first memory cells corresponding to an erasure failed row and inhibiting erasure of second memory cells corresponding to an erasure passed row, and performing an erasure verification by a unit of each row with respect to the first memory cells.

摘要翻译： 本发明构思涉及非易失性存储器件及其操作方法。 非易失性存储器件包括在衬底上以行和列布置的多个串，每个串包括至少一个接地选择晶体管，多个存储器单元和顺序堆叠在衬底上的至少一个串选择晶体管。 该方法包括：擦除对应于擦除失败行的第一存储单元，并禁止对与擦除通过的行相对应的第二存储单元的擦除，并以相对于第一存储单元的每行为单位进行擦除验证。