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    Electronic package structure and the packaging process thereof
    1.
    发明授权
    Electronic package structure and the packaging process thereof 有权
    电子封装结构及其封装过程

    公开(公告)号：US07439619B2

    公开(公告)日：2008-10-21

    申请号：US11028718

    申请日：2005-01-03

    申请人： Chi-Chih Chu ,  Gwo-Liang Weng ,  Shih-Chang Lee

    发明人： Chi-Chih Chu ,  Gwo-Liang Weng ,  Shih-Chang Lee

    IPC分类号： H01L23/34

    CPC分类号： H01L23/564 ,  H01L21/563 ,  H01L24/83 ,  H01L24/90 ,  H01L2224/16 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/83102 ,  H01L2224/83851 ,  H01L2224/90 ,  H01L2224/92125 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/0665 ,  H01L2924/00014 ,  H01L2924/00

    摘要： The present invention provides an electronic packaging process. The surface of the chip carrier includes at least a chip attachment region and a film attachment region adjacent to the chip attachment region. At least a baffle is formed on the surface of the chip carrier, between the chip attachment region and the film attachment region. After attaching the thin film to the film attachment region of the chip carrier through an affixture layer, the chip is electrically and physically connected to the chip attachment region of the chip carrier through an adhesive layer. The baffle can effectively prevent the gas that is released from the adhesive layer from damaging the bonding between the thin film and the affixture layer. Therefore, almost no bubbles are formed and good electrical connection between the thin film and the affixture layer is maintained.

    摘要翻译： 本发明提供一种电子包装方法。 芯片载体的表面至少包括芯片附着区域和与芯片连接区域相邻的膜附着区域。 在芯片载体的表面上，在芯片安装区域和膜附着区域之间形成至少一个挡板。 在通过粘合层将薄膜附着到芯片载体的膜附着区域之后，芯片通过粘合剂层电连接并且物理地连接到芯片载体的芯片连接区域。 挡板可以有效地防止从粘合剂层释放的气体损害薄膜和固定层之间的粘结。 因此，几乎不形成气泡，并且保持薄膜和附着层之间良好的电连接。

    Semiconductor package
    2.
    发明授权
    Semiconductor package 有权
    半导体封装

    公开(公告)号：US07126221B2

    公开(公告)日：2006-10-24

    申请号：US10868495

    申请日：2004-06-14

    申请人： Gwo-Liang Weng ,  Yung-Li Lu ,  Chi-Chih Chu ,  Shih-Chang Lee

    发明人： Gwo-Liang Weng ,  Yung-Li Lu ,  Chi-Chih Chu ,  Shih-Chang Lee

    IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L23/40

    CPC分类号： H05K3/305 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/15311 ,  H05K2201/10734 ,  H05K2203/0545 ,  Y02P70/613 ,  H01L2924/00014

    摘要： A semiconductor package comprising a substrate and a semiconductor device disposed on the substrate by flip-chip bonding. The present invention is characterized by a connection structure disposed between the semiconductor device and the substrate that extends along the periphery of the bottom surface of the semiconductor device. As a result, it can preferably provide additional mounting support between the two. The connection structure can be formed from cured adhesive. The present invention also provides a method of manufacturing the semiconductor package.

    摘要翻译： 一种半导体封装，包括通过倒装芯片接合设置在衬底上的衬底和半导体器件。 本发明的特征在于设置在半导体器件和基板之间的连接结构，该连接结构沿着半导体器件的底表面的周边延伸。 结果，它可以优选地在两者之间提供附加的安装支撑。 连接结构可以由固化的粘合剂形成。 本发明还提供一种半导体封装的制造方法。

    Semiconductor package and method of manufacturing the same
    3.
    发明申请
    Semiconductor package and method of manufacturing the same 有权
    半导体封装及其制造方法

    公开(公告)号：US20050275074A1

    公开(公告)日：2005-12-15

    申请号：US10868495

    申请日：2004-06-14

    申请人： Gwo-Liang Weng ,  Yung-Li Lu ,  Chi-Chih Chu ,  Shih-Chang Lee

    发明人： Gwo-Liang Weng ,  Yung-Li Lu ,  Chi-Chih Chu ,  Shih-Chang Lee

    IPC分类号： H01L23/02 ,  H05K3/30

    CPC分类号： H05K3/305 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/15311 ,  H05K2201/10734 ,  H05K2203/0545 ,  Y02P70/613 ,  H01L2924/00014

    摘要： A semiconductor package comprising a substrate and a semiconductor device disposed on the substrate by flip-chip bonding. The present invention is characterized by a connection structure disposed between the semiconductor device and the substrate that extends along the periphery of the bottom surface of the semiconductor device. As a result, it can preferably provide additional mounting support between the two. The connection structure can be formed from cured adhesive. The present invention also provides a method of manufacturing the semiconductor package.

    摘要翻译： 一种半导体封装，包括通过倒装芯片接合设置在衬底上的衬底和半导体器件。 本发明的特征在于设置在半导体器件和基板之间的连接结构，该连接结构沿着半导体器件的底表面的周边延伸。 结果，它可以优选地在两者之间提供附加的安装支撑。 连接结构可以由固化的粘合剂形成。 本发明还提供一种半导体封装的制造方法。

    Electronic package structure and the packaging process thereof
    4.
    发明申请
    Electronic package structure and the packaging process thereof 有权
    电子封装结构及其封装过程

    公开(公告)号：US20050146054A1

    公开(公告)日：2005-07-07

    申请号：US11028718

    申请日：2005-01-03

    申请人： Chi-Chih Chu ,  Gwo-Liang Weng ,  Shih-Chang Lee

    发明人： Chi-Chih Chu ,  Gwo-Liang Weng ,  Shih-Chang Lee

    IPC分类号： H01L21/48 ,  H01L21/56 ,  H01L21/60 ,  H01L23/00 ,  H01L23/28 ,  H01L23/48

    CPC分类号： H01L23/564 ,  H01L21/563 ,  H01L24/83 ,  H01L24/90 ,  H01L2224/16 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/83102 ,  H01L2224/83851 ,  H01L2224/90 ,  H01L2224/92125 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/0665 ,  H01L2924/00014 ,  H01L2924/00

    摘要： The present invention provides an electronic packaging process. The surface of the chip carrier includes at least a chip attachment region and a film attachment region adjacent to the chip attachment region. At least a baffle is formed on the surface of the chip carrier, between the chip attachment region and the film attachment region. After attaching the thin film to the film attachment region of the chip carrier through an affixture layer, the chip is electrically and physically connected to the chip attachment region of the chip carrier through an adhesive layer. The baffle can effectively prevent the gas that is released from the adhesive layer from damaging the bonding between the thin film and the affixture layer. Therefore, almost no bubbles are formed and good electrical connection between the thin film and the affixture layer is maintained.

    摘要翻译： 本发明提供一种电子包装方法。 芯片载体的表面至少包括芯片附着区域和与芯片连接区域相邻的膜附着区域。 在芯片载体的表面上，在芯片安装区域和膜附着区域之间形成至少一个挡板。 在通过粘合层将薄膜附着到芯片载体的膜附着区域之后，芯片通过粘合剂层电连接并且物理地连接到芯片载体的芯片连接区域。 挡板可以有效地防止从粘合剂层释放的气体损害薄膜和固定层之间的粘结。 因此，几乎不形成气泡，并且保持薄膜和附着层之间良好的电连接。

    SEMICONDUCTOR PACKAGE
    8.
    发明申请
    SEMICONDUCTOR PACKAGE 审中-公开
    半导体封装

    公开(公告)号：US20130161816A1

    公开(公告)日：2013-06-27

    申请号：US13773896

    申请日：2013-02-22

    申请人： Chi-Chih Chu ,  Cheng-Yi Weng

    发明人： Chi-Chih Chu ,  Cheng-Yi Weng

    IPC分类号： H01L23/498

    CPC分类号： H01L23/3128 ,  H01L23/49816 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/32225 ,  H01L2224/48225 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

    摘要： The present invention relates to a semiconductor package. The semiconductor package includes a substrate, at least one chip, a plurality of conductive elements, a plurality of first conductors and a molding compound. The substrate has a plurality of first pads and a solder mask. The first pads are exposed to a first surface of the substrate, and the material of the first pads is copper. The solder mask is disposed on the first surface, contacts the first pads directly, and has at least on opening so as to expose part of the first pads. The chip is mounted on the first surface of the substrate. The conductive elements electrically connect the chip and the substrate. The first conductors are disposed on the first pads. The molding compound is disposed on the first surface of the substrate, and encapsulates the chip, the conductive elements and part of the first conductors. Whereby, the solder mask contacts the first pads directly, and thus results in higher bonding strength, so as to avoid the bridge between the first conductors caused by the first conductors permeating into the interface between the solder mask and the first pads.

    摘要翻译： 本发明涉及一种半导体封装。 半导体封装包括衬底，至少一个芯片，多个导电元件，多个第一导体和模制化合物。 基板具有多个第一焊盘和焊接掩模。 第一焊盘暴露于衬底的第一表面，并且第一焊盘的材料是铜。 焊接掩模设置在第一表面上，直接接触第一焊盘，并且至少具有开口以暴露第一焊盘的部分。 芯片安装在基板的第一表面上。 导电元件电连接芯片和基板。 第一导体设置在第一焊盘上。 模塑料配置在基板的第一表面上，并封装芯片，导电元件和第一导体的一部分。 由此，焊接掩模直接接触第一焊盘，从而导致更高的焊接强度，以避免第一导体之间由第一导体渗入焊料掩模和第一焊盘之间的界面引起的桥。