公开(公告)号：US20070238200A1

公开(公告)日：2007-10-11

申请号：US11556489

申请日：2006-11-03

Applicant: Chia-Lin Chen ,  Y. M. Lin ,  Ming-Chen Chen

Inventor： Chia-Lin Chen ,  Y. M. Lin ,  Ming-Chen Chen

IPC: H01L21/00

CPC classification number: G01R31/2642 ,  G01R31/2858 ,  G01R31/3008

Abstract: A method includes measuring a gate leakage current of a plurality of transistors. A single stress bias voltage is applied to the plurality of transistors. The stress bias voltage causes a 10% degradation in a drive current of each transistor within a respective stress period t. One or more relationships are determined, between the measured gate leakage current and one or more of the group consisting of gate voltage, gate length, gate temperature, and gate width of the plurality of transistors, respectively. A negative bias temperature instability (NBTI) lifetime τ of the plurality of transistors is estimated, based on the measured gate leakage current and the one or more relationships.

Abstract translation: 一种方法包括测量多个晶体管的栅极漏电流。 单个应力偏置电压被施加到多个晶体管。 应力偏置电压在相应的应力周期t内导致每个晶体管的驱动电流10％的劣化。 在测量的栅极漏电流和分别由多个晶体管的栅极电压，栅极长度，栅极温度和栅极宽度的组中的一个或多个之间确定一个或多个关系。 基于所测量的栅极泄漏电流和一个或多个关系，估计多个晶体管的负偏压温度不稳定性（NBTI）寿命ττ。

公开(公告)号：US07820457B2

公开(公告)日：2010-10-26

申请号：US11556489

申请日：2006-11-03

Applicant: Chia-Lin Chen ,  Yi-Miaw Lin ,  Ming-Chen Chen

Inventor： Chia-Lin Chen ,  Yi-Miaw Lin ,  Ming-Chen Chen

IPC: G01R31/26

CPC classification number: G01R31/2642 ,  G01R31/2858 ,  G01R31/3008

Abstract: A method includes measuring a gate leakage current of a plurality of transistors. A single stress bias voltage is applied to the plurality of transistors. The stress bias voltage causes a 10% degradation in a drive current of each transistor within a respective stress period t. One or more relationships are determined, between the measured gate leakage current and one or more of the group consisting of gate voltage, gate length, gate temperature, and gate width of the plurality of transistors, respectively. A negative bias temperature instability (NBTI) lifetime τ of the plurality of transistors is estimated, based on the measured gate leakage current and the one or more relationships.

Abstract translation: 一种方法包括测量多个晶体管的栅极漏电流。 单个应力偏置电压被施加到多个晶体管。 应力偏置电压在相应的应力周期t内导致每个晶体管的驱动电流10％的劣化。 在测量的栅极漏电流和分别由多个晶体管的栅极电压，栅极长度，栅极温度和栅极宽度的组中的一个或多个之间确定一个或多个关系。 基于所测量的栅极泄漏电流和一个或多个关系，估计多个晶体管的负偏置温度不稳定性（NBTI）寿命τ。

公开(公告)号：US07268575B1

公开(公告)日：2007-09-11

申请号：US11278827

申请日：2006-04-06

Applicant: Chia-Lin Chen ,  Ming-Chen Chen

Inventor： Chia-Lin Chen ,  Ming-Chen Chen

IPC: G01R31/26

CPC classification number: G01R31/2642 ,  G01R31/2858 ,  G01R31/3008

Abstract: A method includes measuring a gate leakage current of at least one transistor. A single stress bias voltage is applied to the at least one transistor at a given temperature for a stress period t. The stress bias voltage causes a 10% degradation in a drive current of the transistor at the given temperature within the stress period t. A negative bias temperature instability (NBTI) lifetime τ of the transistor is estimated based on the measured gate leakage current and a relationship between drive current degradation and time observed during the applying step.

Abstract translation: 一种方法包括测量至少一个晶体管的栅极漏电流。 在给定温度下，对于至少一个晶体管施加单个应力偏置电压以施加应力周期t。 应力偏置电压在应力周期t内的给定温度下导致晶体管的驱动电流降低10％。 基于所测量的栅极泄漏电流和驱动电流劣化与施加步骤期间观察到的时间之间的关系来估计晶体管的负偏置温度不稳定性（NBTI）寿命ττ。

公开(公告)号：US08106461B2

公开(公告)日：2012-01-31

申请号：US12887615

申请日：2010-09-22

Applicant: Chia-Lin Chen ,  Yi-Miaw Lin ,  Ming-Chen Chen

Inventor： Chia-Lin Chen ,  Yi-Miaw Lin ,  Ming-Chen Chen

IPC: H01L29/40

CPC classification number: G01R31/2642 ,  G01R31/2858 ,  G01R31/3008

Abstract: An apparatus comprises a circuit for measuring a gate leakage current of a plurality of transistors. A circuit is provided to apply heat to gates of the plurality of transistors. A circuit is provided to apply a single stress bias voltage to the plurality of transistors for a stress period t. The stress bias voltage is sufficient to cause a 10% degradation in a drive current of the transistor within the stress period t. A processor is provided for estimating a negative bias temperature instability (NBTI) lifetime τ of the transistor based on a relationship between the gate leakage current and one or more of the group consisting of gate voltage, gate length, gate temperature, and gate width of the plurality of transistors. The relationship is determined from data observed while applying the single stress bias voltage.

Abstract translation: 一种装置包括用于测量多个晶体管的栅极漏电流的电路。 提供电路以向多个晶体管的栅极施加热量。 提供电路以在单个应力偏置电压施加到多个晶体管的应力周期t。 应力偏置电压足以在应力周期t内导致晶体管的驱动电流10％的降低。 提供一种处理器，用于基于栅极泄漏电流与栅极电压，栅极长度，栅极温度和栅极宽度之间的一个或多个的关系来估计晶体管的负偏置温度不稳定性（NBTI）寿命τ 多个晶体管。 该关系是从应用单个应力偏置电压时观察到的数据确定的。

公开(公告)号：US10683978B2

公开(公告)日：2020-06-16

申请号：US16001920

申请日：2018-06-06

Applicant: Chia-Lin Chen

Inventor： Chia-Lin Chen

IPC: F21S8/04 ,  F21K9/20 ,  F21V19/00 ,  F21S8/00 ,  F21V3/02 ,  F21Y105/18 ,  F21Y115/10 ,  F21V21/002 ,  H01R33/94 ,  H02G3/20 ,  H01R33/46 ,  F16M13/02

Abstract: A lamp power assembling structure and method, the lamp power assembling structure is installed indoors and is connected an indoor power source, and includes a lamp power seat and a lamp fixing seat. The lamp power seat has a first power connector for connecting to the indoor power source and two sliding trenches. Each sliding trench has an arced channel and an enlarged hole formed at an end of the arced channel. The lamp fixing seat has a second power connector corresponding to the first power connector and two fasteners separately corresponding to the two enlarged holes. The two fasteners are separately inserted into the two enlarged holes, and the lamp fixing seat is rotated about the first and second power connectors so as to make the two fasteners separately to be engaged with the arced channels to fix the lamp fixing seat to the lamp power seat.

公开(公告)号：US20190022835A1

公开(公告)日：2019-01-24

申请号：US16143413

申请日：2018-09-26

Applicant: Chia-Lin Chen

Inventor： Chia-Lin Chen

IPC: B25B23/12 ,  B25B13/06 ,  B25B23/00

Abstract: A socket contains: a body, a push member, and a reverse pushing structure. The body includes a connecting section and a fitting section, the connecting section has a first polygonal orifice configured to accommodate a socket wrench, and the fitting section has a second polygonal orifice for driving a fastener element. The body includes a receiving groove defined therein communicating with the second polygonal orifice, and the push member is movably accommodated in the second polygonal orifice and includes at least one magnetic attraction element. The reverse pushing structure is housed in the receiving groove and configured to push the push member toward the rim of the second polygonal orifice.

公开(公告)号：US07579859B2

公开(公告)日：2009-08-25

申请号：US11763077

申请日：2007-06-14

Applicant: Pei-Chun Liao ,  Chia-Lin Chen

Inventor： Pei-Chun Liao ,  Chia-Lin Chen

IPC: G01R31/26

CPC classification number: G01R31/2858 ,  G01R31/129 ,  G01R31/2623

Abstract: The current invention provides a method of determining the lifetime of a semiconductor device due to time dependent dielectric breakdown (TDDB). This method includes providing a plurality of samples of dielectric layer disposed as a gate dielectric layer of a MOS transistor, approximating a source/drain current density distribution as a first function of voltage applied on the samples, approximating a substrate current density distribution as a second function of voltage applied on the samples, approximating a dielectric layer lifetime distribution as a third function of source/drain current density and substrate current density in the samples, deriving, from the first, the second, and the third functions, an empirical model wherein a dielectric layer lifetime is a function of voltage applied thereon, and using the model to determine dielectric layer lifetime at a pre-determined operating gate voltage.

Abstract translation: 本发明提供一种由于时间依赖介电击穿（TDDB）确定半导体器件的寿命的方法。 该方法包括提供设置为MOS晶体管的栅介质层的介质层的多个样本，其近似源/漏电流密度分布作为施加在样本上的电压的第一函数，将基板电流密度分布近似为第二 作为施加在样品上的电压的函数，近似作为源/漏电流密度和样品中的衬底电流密度的第三函数的介电层寿命分布，从第一，第二和第三函数导出经验模型，其中 介电层寿命是施加在其上的电压的函数，并且使用该模型来确定在预定的工作栅极电压下的介电层寿命。

公开(公告)号：US20080318378A1

公开(公告)日：2008-12-25

申请号：US11765971

申请日：2007-06-20

Applicant: Chih-Ta Wu ,  Jason Lee ,  Chung Chien Wang ,  Hsing-Lien Lin ,  Yu-Jen Wang ,  Yeur-Luen Tu ,  Chern-Yow Hsu ,  Yuan-Hung Liu ,  Chi-Hsin Lo ,  Chia-Shiung Tsai ,  Lucy Chang ,  Chia-Lin Chen ,  Ming-Chih Tsai

Inventor： Chih-Ta Wu ,  Jason Lee ,  Chung Chien Wang ,  Hsing-Lien Lin ,  Yu-Jen Wang ,  Yeur-Luen Tu ,  Chern-Yow Hsu ,  Yuan-Hung Liu ,  Chi-Hsin Lo ,  Chia-Shiung Tsai ,  Lucy Chang ,  Chia-Lin Chen ,  Ming-Chih Tsai

IPC: H01L21/20 ,  H01L21/8242

CPC classification number: H01L27/10814 ,  H01L27/10852 ,  H01L28/40 ,  H01L28/75

Abstract: A capacitor and methods for forming the same are provided. The method includes forming a bottom electrode; treating the bottom electrode in an oxygen-containing environment to convert a top layer of the bottom electrode into a buffer layer; forming an insulating layer on the buffer layer; and forming a top electrode over the insulating layer.

Abstract translation: 提供电容器及其形成方法。 该方法包括形成底部电极; 在含氧环境中处理底部电极以将底部电极的顶层转化为缓冲层; 在缓冲层上形成绝缘层; 并在所述绝缘层上形成顶部电极。

公开(公告)号：US07453280B1

公开(公告)日：2008-11-18

申请号：US11896364

申请日：2007-08-31

Applicant: Sheng-Hui Liang ,  Chia-Lin Chen ,  Pei-Chun Liao ,  Chin-Yuan Ko

Inventor： Sheng-Hui Liang ,  Chia-Lin Chen ,  Pei-Chun Liao ,  Chin-Yuan Ko

IPC: G01R31/26 ,  G01R31/28

CPC classification number: G01R31/2623 ,  G01R31/2831 ,  G01R31/2894 ,  G11C11/41 ,  G11C29/006 ,  G11C29/50 ,  G11C2029/0403 ,  G11C2029/5002 ,  G11C2029/5006

Abstract: A method for testing a batch of semiconductor devices in wafer level is provided. The method includes the following steps: (a) obtaining a breakdown voltage of gate dielectric of each semiconductor device; (b) applying, to the gate dielectric of each semiconductor device, a stress voltage below the breakdown voltage but above a base voltage of gate dielectric of the semiconductor devices; (c) after the step (b), measuring currents of gate dielectric of each semiconductor devices at the base voltage; and (d) obtaining a tailing distribution from the measured currents.

Abstract translation: 提供了一种用于测试晶片级的一批半导体器件的方法。 该方法包括以下步骤：（a）获得每个半导体器件的栅极电介质的击穿电压; （b）向每个半导体器件的栅极电介质施加低于击穿电压但高于半导体器件的栅极电介质的基极电压的应力电压; （c）在步骤（b）之后，测量每个半导体器件在基极电压下的栅极电介质的电流; 和（d）从测量的电流获得拖尾分布。

公开(公告)号：US07316970B2

公开(公告)日：2008-01-08

申请号：US10892014

申请日：2004-07-14

Applicant: Chien-Hao Chen ,  Ju-Wang Hsu ,  Chia-Lin Chen ,  Tze-Liang Lee ,  Shih-Chang Chen

Inventor： Chien-Hao Chen ,  Ju-Wang Hsu ,  Chia-Lin Chen ,  Tze-Liang Lee ,  Shih-Chang Chen

IPC: H01L21/425

CPC classification number: H01L21/31111 ,  H01L21/823481 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/78

Abstract: A method for forming a resist protect layer on a semiconductor substrate includes the following steps. An isolation structure is formed on the semiconductor substrate. An original nitride layer having a substantial etch selectivity to the isolation structure is formed over the semiconductor substrate. A photoresist mask is formed for partially covering the original nitride layer. A wet etching is performed to remove the original nitride layer uncovered by the photoresist mask in such a way without causing substantial damage to the isolation structure. As such, the original nitride layer covered by the photoresist mask constitutes the resist protect layer.

Abstract translation: 在半导体衬底上形成抗蚀剂保护层的方法包括以下步骤。 在半导体衬底上形成隔离结构。 在半导体衬底上形成对隔离结构具有实质蚀刻选择性的原始氮化物层。 形成光致抗蚀剂掩模以部分覆盖原始氮化物层。 执行湿蚀刻以以这样的方式去除由光致抗蚀剂掩模未覆盖的原始氮化物层，而不会对隔离结构造成实质损坏。 因此，由光致抗蚀剂掩模覆盖的原始氮化物层构成抗蚀剂保护层。