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    Method for forming a cantilever and tip
    1.
    发明授权
    Method for forming a cantilever and tip 失效
    形成悬臂和尖端的方法

    公开(公告)号：US07494593B1

    公开(公告)日：2009-02-24

    申请号：US10879971

    申请日：2004-06-28

    申请人： Chien-Hua Chen ,  John Chen ,  Sriram Ramamoorthi

    发明人： Chien-Hua Chen ,  John Chen ,  Sriram Ramamoorthi

    IPC分类号： C25F3/12

    CPC分类号： B81C1/0015 ,  B81B2201/07

    摘要： A method is disclosed for forming a single crystal cantilever and tip on a substrate. The method can include the operation of defining an implant area on the substrate with a layer of photoresist. A further operation can be implanting oxygen into the substrate in the implant area to a predetermined depth to form a buried oxide layer. The buried oxide layer can define a bottom of the single crystal cantilever and tip. Another operation can involve shaping the single crystal cantilever and tip from the substrate above the buried oxide layer.

    摘要翻译： 公开了一种用于在基板上形成单晶悬臂和尖端的方法。 该方法可以包括在衬底上用光致抗蚀剂层限定植入区域的操作。 进一步的操作可以是将植入区域中的氧注入到预定深度的衬底中以形成掩埋氧化物层。 掩埋氧化物层可以限定单晶悬臂和尖端的底部。 另外的操作可以包括从掩埋氧化物层上方的衬底上形成单晶悬臂和尖端。

    Sofa bed
    4.
    外观设计
    Sofa bed 有权

    公开(公告)号：USD979956S1

    公开(公告)日：2023-03-07

    申请号：US29811123

    申请日：2021-10-12

    申请人： John Chen

    设计人： John Chen

    Hammer
    5.
    外观设计
    Hammer 有权

    公开(公告)号：USD795667S1

    公开(公告)日：2017-08-29

    申请号：US29521097

    申请日：2015-03-19

    申请人： John Chen

    设计人： John Chen

    Top drain LDMOS
    6.
    发明授权
    Top drain LDMOS 有权
    顶级漏极LDMOS

    公开(公告)号：US09159828B2

    公开(公告)日：2015-10-13

    申请号：US13436308

    申请日：2012-03-30

    申请人： Shekar Mallikarjunaswamy ,  John Chen ,  YongZhong Hu

    发明人： Shekar Mallikarjunaswamy ,  John Chen ,  YongZhong Hu

    IPC分类号： H01L29/78 ,  H01L29/417 ,  H01L29/66 ,  H01L29/06 ,  H01L29/10 ,  H01L29/40 ,  H01L29/45

    CPC分类号： H01L29/7835 ,  H01L29/0692 ,  H01L29/1083 ,  H01L29/161 ,  H01L29/402 ,  H01L29/4175 ,  H01L29/41766 ,  H01L29/456 ,  H01L29/66659 ,  H01L29/66681

    摘要： In an embodiment, this invention discloses a top-drain lateral diffusion metal oxide field effect semiconductor (TD-LDMOS) device supported on a semiconductor substrate. The TD-LDMOS includes a source electrode disposed on a bottom surface of the semiconductor substrate. The TD-LDMOS further includes a source region and a drain region disposed on two opposite sides of a planar gate disposed on a top surface of the semiconductor substrate wherein the source region is encompassed in a body region constituting a drift region as a lateral current channel between the source region and drain region under the planar gate. The TD-LDMOS further includes at least a trench filled with a conductive material and extending vertically from the body region near the top surface downwardly to electrically contact the source electrode disposed on the bottom surface of the semiconductor substrate.

    摘要翻译： 在一个实施例中，本发明公开了一种支撑在半导体衬底上的顶排侧向扩散金属氧化物场效应半导体（TD-LDMOS）器件。 TD-LDMOS包括设置在半导体衬底的底表面上的源电极。 TD-LDMOS还包括设置在设置在半导体衬底的顶表面上的平面栅极的两个相对侧上的源极区域和漏极区域，其中源极区域包围在构成漂移区域的体区域中作为横向电流通道 在平面栅极下面的源极区域和漏极区域之间。 TD-LDMOS还包括至少填充有导电材料并且从顶表面附近的主体区域向下垂直延伸的沟槽，以电接触设置在半导体衬底的底表面上的源电极。

    Direct contact in trench with three-mask shield gate process
    7.
    发明授权
    Direct contact in trench with three-mask shield gate process 有权
    直接接触沟槽与三屏蔽屏蔽门工艺

    公开(公告)号：US08847306B2

    公开(公告)日：2014-09-30

    申请号：US13343666

    申请日：2012-01-04

    申请人： Sung-Shan Tai ,  Hamza Yilmaz ,  Anup Bhalla ,  Hong Chang ,  John Chen

    发明人： Sung-Shan Tai ,  Hamza Yilmaz ,  Anup Bhalla ,  Hong Chang ,  John Chen

    IPC分类号： H01L29/66 ,  H01L21/336 ,  H01L29/423 ,  H01L29/78 ,  H01L29/40 ,  H01L29/45 ,  H01L29/49 ,  H01L29/08 ,  H01L21/265

    CPC分类号： H01L29/7813 ,  H01L21/26586 ,  H01L29/0869 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/4238 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7811

    摘要： A semiconductor substrate may be etched to form trenches with three different widths. A first conductive material is formed at the bottom of the trenches. A second conductive material separated by an insulator is formed over the first conductive material. A first insulator layer is formed on the trenches. A body layer is formed in the substrate. A source is formed in the body layer. A second insulator layer is formed on the trenches and source. Source and gate contacts are formed through the second insulator layer. Source and gate metal are formed on the second insulator layer. This abstract is provided to comply with rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

    摘要翻译： 可以蚀刻半导体衬底以形成具有三个不同宽度的沟槽。 第一导电材料形成在沟槽的底部。 在第一导电材料上方形成由绝缘体隔开的第二导电材料。 在沟槽上形成第一绝缘体层。 在衬底中形成体层。 源体形成在体层中。 在沟槽和源极上形成第二绝缘体层。 源极和栅极触点通过第二绝缘体层形成。 源极和栅极金属形成在第二绝缘体层上。 提供该摘要以符合要求抽象的规则，允许搜索者或其他读者快速确定技术公开内容的主题。 提交它的理解是，它不会用于解释或限制权利要求的范围或含义。

    Trench poly ESD formation for trench MOS and SGT
    9.
    发明授权
    Trench poly ESD formation for trench MOS and SGT 有权
    沟槽MOS和SGT的沟槽聚合物ESD形成

    公开(公告)号：US08772828B2

    公开(公告)日：2014-07-08

    申请号：US13911871

    申请日：2013-06-06

    申请人： Hong Chang ,  John Chen

    发明人： Hong Chang ,  John Chen

    IPC分类号： H01L29/78

    CPC分类号： H01L29/7393 ,  H01L27/0259 ,  H01L29/7827

    摘要： A semiconductor device includes a semiconductor material disposed in a trench with polysilicon lining at least the bottom of the trench. The semiconductor material includes differently doped regions configured as a PNP or NPN structure formed in the trench with differently doped regions located side by side across a width of the trench. It is emphasized that this abstract is provided to comply with rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

    摘要翻译： 半导体器件包括设置在具有至少沟槽底部的多晶硅衬底的沟槽中的半导体材料。 半导体材料包括不同的掺杂区域，其被配置为在沟槽中形成的PNP或NPN结构，其中不同的掺杂区域跨越沟槽的宽度并排设置。 要强调的是，提供这个摘要是为了符合要求摘要的规则，允许搜索者或其他读者快速确定技术公开内容的主题。 提交它的理解是，它不会用于解释或限制权利要求的范围或含义。

    Shielded gate trench MOSFET with increased source-metal contact
    10.
    发明授权
    Shielded gate trench MOSFET with increased source-metal contact 有权
    屏蔽栅极沟槽MOSFET增加了源极 - 金属接触

    公开(公告)号：US08618601B2

    公开(公告)日：2013-12-31

    申请号：US13016804

    申请日：2011-01-28

    申请人： John Chen

    发明人： John Chen

    IPC分类号： H01L29/66

    CPC分类号： H01L29/4236 ,  H01L21/26513 ,  H01L21/26586 ,  H01L29/0847 ,  H01L29/0865 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/42372 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/66666 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7813 ,  H01L29/7827

    摘要： A semiconductor device formed on a semiconductor substrate having a substrate top surface, includes: a gate trench extending from the substrate top surface into the semiconductor substrate; a gate electrode in the gate trench; a dielectric material disposed over the gate electrode; a body region adjacent to the gate trench; a source region embedded in the body region, at least a portion of the source region extending above the dielectric material; a contact trench that allows contact such as electrical contact between the source region and the body region; and a metal layer disposed over at least a portion of a gate trench opening, at least a portion of the source region, and at least a portion of the contact trench.

    摘要翻译： 一种半导体器件，形成在具有衬底顶表面的半导体衬底上，包括：从衬底顶表面延伸到半导体衬底中的栅极沟槽; 栅极沟槽中的栅电极; 设置在所述栅电极上的电介质材料; 与栅极沟槽相邻的体区; 源区域，其嵌入在所述体区中，所述源极区域的至少一部分延伸到所述介电材料之上; 接触沟槽，其允许诸如源极区域和身体区域之间的电接触的接触; 以及设置在栅极沟槽开口的至少一部分，源极区的至少一部分以及接触沟槽的至少一部分之上的金属层。