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61 条记录 (耗时 0.033 秒)

    Method and apparatus for feedback-based resistance calibration
    1.
    发明授权
    Method and apparatus for feedback-based resistance calibration 有权
    用于基于反馈的电阻校准的方法和装置

    公开(公告)号：US09134360B2

    公开(公告)日：2015-09-15

    申请号：US13547101

    申请日：2012-07-12

    申请人： Tao Wen Chung ,  Chan-Hong Chern ,  Ming-Chieh Huang ,  Chih-Chang Lin ,  Yuwen Swei

    发明人： Tao Wen Chung ,  Chan-Hong Chern ,  Ming-Chieh Huang ,  Chih-Chang Lin ,  Yuwen Swei

    IPC分类号： H03L5/00 ,  G01R31/26

    CPC分类号： G01R31/2621

    摘要： A circuit has a first circuit module including a first resistor and first and second transistors coupled in parallel with the first resistor. The first resistor and the first and second transistors are coupled together at a first node. An equivalent resistance across the first circuit module increases as a voltage of the first node is increased from a first voltage to a second voltage, and the equivalent resistance across the first circuit module decreases as the voltage of the first node is increased from the second voltage to a third voltage.

    摘要翻译： 电路具有包括第一电阻器和与第一电阻器并联耦合的第一和第二晶体管的第一电路模块。 第一电阻器和第一和第二晶体管在第一节点耦合在一起。 当第一节点的电压从第一电压增加到第二电压时，跨第一电路模块的等效电阻增加，并且第一电路模块上的等效电阻随着第一节点的电压从第二电压增加而减小 到第三电压。

    Drivers having T-coil structures
    2.
    发明授权
    Drivers having T-coil structures 有权
    驱动器具有T型线圈结构

    公开(公告)号：US08896352B2

    公开(公告)日：2014-11-25

    申请号：US13278742

    申请日：2011-10-21

    申请人： Ming-Chieh Huang ,  Tao Wen Chung ,  Chan-Hong Chern ,  Chih-Chang Lin ,  Yuwen Swei ,  Chiang Pu

    发明人： Ming-Chieh Huang ,  Tao Wen Chung ,  Chan-Hong Chern ,  Chih-Chang Lin ,  Yuwen Swei ,  Chiang Pu

    IPC分类号： H03K3/00

    CPC分类号： H03H11/44 ,  H01S5/0427 ,  H04B10/504

    摘要： A driver includes a first driver stage having at least one input node and at least one first output node. The first driver stage includes a T-coil structure that is disposed adjacent to the at least one first output node. The T-coil structure includes a first set of inductors each being operable to provide a first inductance. A second set of inductors are electrically coupled with the first set of inductors in a parallel fashion. The second set of inductors each are operable to provide a second inductance. A second driver stage is electrically coupled with the first driver stage.

    摘要翻译： 驱动器包括具有至少一个输入节点和至少一个第一输出节点的第一驱动器级。 第一驱动级包括邻近于至少一个第一输出节点设置的T型线圈结构。 T型线圈结构包括第一组电感器，每个电感器可操作以提供第一电感。 第二组电感器以并行方式与第一组电感器电耦合。 第二组电感器可操作以提供第二电感。 第二驱动级与第一驱动器级电耦合。

    Capactive load PLL with calibration loop
    3.
    发明授权
    Capactive load PLL with calibration loop 有权
    带校准回路的负载负载PLL

    公开(公告)号：US08816732B2

    公开(公告)日：2014-08-26

    申请号：US13530136

    申请日：2012-06-22

    申请人： Chan-Hong Chern ,  Tao Wen Chung ,  Ming-Chieh Huang ,  Chih-Chang Lin ,  Tsung-Ching Huang ,  Fu-Lung Hsueh

    发明人： Chan-Hong Chern ,  Tao Wen Chung ,  Ming-Chieh Huang ,  Chih-Chang Lin ,  Tsung-Ching Huang ,  Fu-Lung Hsueh

    IPC分类号： H03L7/06

    CPC分类号： H03L7/103 ,  H03L7/097 ,  H03L7/0995 ,  H03L7/1072 ,  H03L7/18 ,  H03L2207/06

    摘要： A circuit includes a capacitive-load voltage controlled oscillator having an input configured to receive a first input signal and an output configured to output an oscillating output signal. A calibration circuit is coupled to the voltage controlled oscillator and is configured to output one or more control signals to the capacitive-load voltage controlled oscillator for adjusting a frequency of the oscillating output signal. The calibration circuit is configured to output the one or more control signals in response to a comparison of an input voltage to at least one reference voltage.

    摘要翻译： 电路包括电容负载压控振荡器，其具有被配置为接收第一输入信号的输入和被配置为输出振荡输出信号的输出。 校准电路耦合到压控振荡器，并被配置为将一个或多个控制信号输出到电容负载压控振荡器，用于调整振荡输出信号的频率。 校准电路被配置为响应于输入电压与至少一个参考电压的比较而输出一个或多个控制信号。

    Automatic Misalignment Balancing Scheme for Multi-Patterning Technology
    4.
    发明申请
    Automatic Misalignment Balancing Scheme for Multi-Patterning Technology 有权
    多图案化技术的自动对准平衡方案

    公开(公告)号：US20140038085A1

    公开(公告)日：2014-02-06

    申请号：US13562436

    申请日：2012-07-31

    申请人： Chan-Hong Chern ,  Tao Wen Chung ,  Ming-Chieh Huang ,  Chih-Chang Lin ,  Tsung-Ching (Jim) Huang ,  Fu-Lung Hsueh

    发明人： Chan-Hong Chern ,  Tao Wen Chung ,  Ming-Chieh Huang ,  Chih-Chang Lin ,  Tsung-Ching (Jim) Huang ,  Fu-Lung Hsueh

    IPC分类号： G06F17/50 ,  G03F1/68

    CPC分类号： G03F7/70466 ,  G03F7/70433 ,  G06F17/5077

    摘要： Some aspects of the present disclosure provide for a method of automatically balancing mask misalignment for multiple patterning layers to minimize the consequences of mask misalignment. In some embodiments, the method defines a routing grid for one or more double patterning layers within an IC layout. The routing grid has a plurality of vertical grid lines extending along a first direction and a plurality of horizontal grid lines extending along a second, orthogonal direction. Alternating lines of the routing grid in a given direction (e.g., the horizontal and vertical direction) are assigned different colors. Shapes on the double patterning layers are then routed along the routing grid in a manner that alternates between different colored grid lines. By routing in such a manner, variations in capacitive coupling caused by mask misalignment are reduced.

    摘要翻译： 本公开的一些方面提供了一种自动平衡多个图案化层的掩模未对准的方法，以最小化掩模未对准的后果。 在一些实施例中，该方法定义了IC布局内的一个或多个双图案化层的布线网格。 路由网格具有沿着第一方向延伸的多个垂直网格线和沿着第二正交方向延伸的多个水平网格线。 在给定方向（例如，水平和垂直方向）上布线网格的交替线被分配不同的颜色。 然后双重图案化层上的形状沿着布线网格以不同颜色的网格线之间交替的方式布线。 通过以这种方式进行布线，减少了由掩模未对准引起的电容耦合的变化。

    Voltage level shifter
    6.
    发明授权
    Voltage level shifter 有权
    电压电平转换器

    公开(公告)号：US08854104B2

    公开(公告)日：2014-10-07

    申请号：US13793681

    申请日：2013-03-11

    申请人： Tao Wen Chung ,  Chan-Hong Chern ,  Tsung-Ching (Jim) Huang ,  Chih-Chang Lin ,  Ming-Chieh Huang

    发明人： Tao Wen Chung ,  Chan-Hong Chern ,  Tsung-Ching (Jim) Huang ,  Chih-Chang Lin ,  Ming-Chieh Huang

    IPC分类号： H03L5/00

    CPC分类号： H03L5/00 ,  H03K3/356182 ,  H03K17/102 ,  H03K19/018521

    摘要： A circuit includes a first capacitive device and a first latch. The first capacitive device includes a first end configured to receive a first input signal and a second end coupled with the first latch. The first latch includes a first transistor and a second transistor that are of a first type. A first terminal of the first transistor and a first terminal of the second transistor are each configured to receive a first voltage value. A second terminal of the first transistor is coupled with a third terminal of the second transistor. A third terminal of the first transistor is coupled with a second terminal of the second transistor and with the second end of the capacitive device, and is configured to provide an output voltage for the first latch.

    摘要翻译： 电路包括第一电容性装置和第一锁存器。 第一电容性装置包括被配置为接收第一输入信号的第一端和与第一锁存器耦合的第二端。 第一锁存器包括第一类型的第一晶体管和第二晶体管。 第一晶体管的第一端子和第二晶体管的第一端子都被配置为接收第一电压值。 第一晶体管的第二端与第二晶体管的第三端耦合。 第一晶体管的第三端子与第二晶体管的第二端子和电容器件的第二端耦合，并且被配置为提供用于第一锁存器的输出电压。

    Multiple-phase clock generator
    8.
    发明授权
    Multiple-phase clock generator 有权
    多相时钟发生器

    公开(公告)号：US08884665B2

    公开(公告)日：2014-11-11

    申请号：US13084817

    申请日：2011-04-12

    申请人： Chih-Chang Lin ,  Chan-Hong Chern ,  Ming-Chieh Huang ,  Tao Wen Chung

    发明人： Chih-Chang Lin ,  Chan-Hong Chern ,  Ming-Chieh Huang ,  Tao Wen Chung

    IPC分类号： H03B19/00 ,  H03K5/15

    CPC分类号： H03K5/15013

    摘要： A multiple-phase clock generator includes at least one stage of dividers. A clock signal is supplied as a first stage clock input to dividers in a first stage of dividers. An N-th stage includes 2N dividers, where N is a positive integer number. Each divider in the first stage is configured to divide a first clock frequency of the first stage clock input by 2 to provide a first stage output. Each divider in the N-th stage is configured to divide an N-th clock frequency of an N-th stage clock input by 2 to provide an N-th stage output. The N-th stage outputs from the dividers in the N-th stage provide 2N-phase clock signals that are equally distributed with a same phase difference between adjacent phase clock signals.

    摘要翻译： 多相时钟发生器包括至少一个分频器级。 时钟信号作为第一级时钟输入提供给分频器的第一级中的分频器。 第N级包括2N个分频器，其中N是正整数。 第一级中的每个分频器被配置为将第一级时钟输入的第一时钟频率除以2以提供第一级输出。 第N级中的每个除法器被配置为将输入的第N级时钟的第N个时钟频率除以2以提供第N级输出。 在第N级的分频器的第N级输出提供2N相位时钟信号，它们在相邻的相位时钟信号之间以相同的相位差均匀分布。

    Decision feedback equalizer
    10.
    发明授权
    Decision feedback equalizer 有权
    决策反馈均衡器

    公开(公告)号：US08862951B2

    公开(公告)日：2014-10-14

    申请号：US13528877

    申请日：2012-06-21

    申请人： Ming-Chieh Huang ,  Chan-Hong Chern ,  Tao Wen Chung ,  Yuwen Swei ,  Chih-Chang Lin ,  Tsung-Ching Huang

    发明人： Ming-Chieh Huang ,  Chan-Hong Chern ,  Tao Wen Chung ,  Yuwen Swei ,  Chih-Chang Lin ,  Tsung-Ching Huang

    IPC分类号： G06F11/00 ,  H04L27/01

    CPC分类号： H04L25/03057 ,  H04L25/06 ,  H04L25/08

    摘要： A circuit includes a summation circuit for receiving an input data signal and a feedback signal including a previous data bit. The summation circuit is configured to output a conditioned input data signal to a clock and data recovery circuit. A first flip-flop is coupled to an output of the summation circuit and is configured to receive a first set of bits of the conditioned input data signal and a first clock signal having a frequency that is less than a frequency at which the input data signal is received by the first summation circuit. A second flip-flop is coupled to the output of the summation circuit and is configured to receive a second set of bits of the conditioned input data signal and a second clock signal having a frequency that is less than the frequency at which the input data signal is received by the first summation circuit.

    摘要翻译： 电路包括用于接收输入数据信号和包括先前数据位的反馈信号的求和电路。 求和电路被配置为将调节的输入数据信号输出到时钟和数据恢复电路。 第一触发器耦合到求和电路的输出，并且被配置为接收经调节的输入数据信号的第一比特组和具有小于输入数据信号的频率的频率的第一时钟信号 由第一求和电路接收。 第二触发器耦合到求和电路的输出，并且被配置为接收经调节的输入数据信号的第二组比特和具有小于输入数据信号的频率的频率的第二时钟信号 由第一求和电路接收。