公开(公告)号：US20120313175A1

公开(公告)日：2012-12-13

申请号：US13156352

申请日：2011-06-09

申请人： Chih-Chung Wang ,  Wei-Lun Hsu ,  Te-Yuan Wu ,  Wen-Fang Lee ,  Ke-Feng Lin ,  Shan-Shi Huang ,  Ming-Tsung Lee

发明人： Chih-Chung Wang ,  Wei-Lun Hsu ,  Te-Yuan Wu ,  Wen-Fang Lee ,  Ke-Feng Lin ,  Shan-Shi Huang ,  Ming-Tsung Lee

IPC分类号： H01L27/06

CPC分类号： H01L27/0277 ,  H01L21/761 ,  H01L21/823481 ,  H01L21/823493 ,  H01L27/0623 ,  H01L27/0922

摘要： The present invention provides a semiconductor device including a substrate, a deep well, a high-voltage well, and a doped region. The substrate and the high-voltage well have a first conductive type, and the deep well and the doped region have a second conductive type different from the first conductive type. The substrate has a high-voltage region and a low-voltage region, and the deep well is disposed in the substrate in the high-voltage region. The high-voltage well is disposed in the substrate between the high-voltage region and the low-voltage region, and the doped region is disposed in the high-voltage well. The doped region and the high-voltage well are electrically connected to a ground.

摘要翻译： 本发明提供一种包括衬底，深阱，高压阱和掺杂区的半导体器件。 衬底和高压阱具有第一导电类型，并且深阱和掺杂区具有不同于第一导电类型的第二导电类型。 衬底具有高电压区域和低电压区域，并且深阱设置在高压区域中的衬底中。 高电压阱设置在高电压区域和低电压区域之间的衬底中，掺杂区域设置在高压阱中。 掺杂区和高电压阱电连接到地。

公开(公告)号：US08698247B2

公开(公告)日：2014-04-15

申请号：US13156352

申请日：2011-06-09

申请人： Chih-Chung Wang ,  Wei-Lun Hsu ,  Te-Yuan Wu ,  Wen-Fang Lee ,  Ke-Feng Lin ,  Shan-Shi Huang ,  Ming-Tsung Lee

发明人： Chih-Chung Wang ,  Wei-Lun Hsu ,  Te-Yuan Wu ,  Wen-Fang Lee ,  Ke-Feng Lin ,  Shan-Shi Huang ,  Ming-Tsung Lee

IPC分类号： H01L23/62

CPC分类号： H01L27/0277 ,  H01L21/761 ,  H01L21/823481 ,  H01L21/823493 ,  H01L27/0623 ,  H01L27/0922

摘要： The present invention provides a semiconductor device including a substrate, a deep well, a high-voltage well, and a doped region. The substrate and the high-voltage well have a first conductive type, and the deep well and the doped region have a second conductive type different from the first conductive type. The substrate has a high-voltage region and a low-voltage region, and the deep well is disposed in the substrate in the high-voltage region. The high-voltage well is disposed in the substrate between the high-voltage region and the low-voltage region, and the doped region is disposed in the high-voltage well. The doped region and the high-voltage well are electrically connected to a ground.

摘要翻译： 本发明提供一种包括衬底，深阱，高压阱和掺杂区的半导体器件。 衬底和高压阱具有第一导电类型，并且深阱和掺杂区具有不同于第一导电类型的第二导电类型。 衬底具有高电压区域和低电压区域，并且深阱设置在高压区域中的衬底中。 高电压阱设置在高电压区域和低电压区域之间的衬底中，掺杂区域设置在高压阱中。 掺杂区和高电压阱电连接到地。

公开(公告)号：US08436418B2

公开(公告)日：2013-05-07

申请号：US13163734

申请日：2011-06-20

申请人： Chih-Chung Wang ,  Wei-Lun Hsu ,  Te-Yuan Wu ,  Ke-Feng Lin ,  Shan-Shi Huang ,  Ming-Tsung Lee ,  Wen-Fang Lee

发明人： Chih-Chung Wang ,  Wei-Lun Hsu ,  Te-Yuan Wu ,  Ke-Feng Lin ,  Shan-Shi Huang ,  Ming-Tsung Lee ,  Wen-Fang Lee

IPC分类号： H01L29/94

CPC分类号： H01L27/0251 ,  H01L27/0266 ,  H01L29/0634 ,  H01L29/1087 ,  H01L29/404 ,  H01L29/42368 ,  H01L29/7817 ,  H01L29/7835 ,  H01L29/7838 ,  H01L29/861

摘要： The present invention provides a high-voltage semiconductor device including a deep well, a first doped region disposed in the deep well, a high-voltage well, a second doped region disposed in the high-voltage well, a first gate structure disposed on the high-voltage well between the second doped region and the first doped region, a doped channel region disposed in the high-voltage region and in contact with the second doped region and the deep well, and a third doped region disposed in the high-voltage well. The high-voltage well has a first conductive type, and the deep well, the first doped region, the second doped region, the doped channel region, and the third doped region have a second conductive type different from the first conductive type.

摘要翻译： 本发明提供了一种高压半导体器件，包括深阱，设置在深阱中的第一掺杂区，高电压阱，设置在高压阱中的第二掺杂区，设置在高阱上的第一栅极结构 在所述第二掺杂区域和所述第一掺杂区域之间的高电压阱，设置在所述高压区域中并与所述第二掺杂区域和所述深阱接触的掺杂沟道区域，以及设置在所述高压区域中的第三掺杂区域 好。 高电压阱具有第一导电类型，并且深阱，第一掺杂区域，第二掺杂区域，掺杂沟道区域和第三掺杂区域具有不同于第一导电类型的第二导电类型。

公开(公告)号：US20120319189A1

公开(公告)日：2012-12-20

申请号：US13163734

申请日：2011-06-20

申请人： Chih-Chung Wang ,  Wei-Lun Hsu ,  Te-Yuan Wu ,  Ke-Feng Lin ,  Shan-Shi Huang ,  Ming-Tsung Lee ,  Wen-Fang Lee

发明人： Chih-Chung Wang ,  Wei-Lun Hsu ,  Te-Yuan Wu ,  Ke-Feng Lin ,  Shan-Shi Huang ,  Ming-Tsung Lee ,  Wen-Fang Lee

IPC分类号： H01L29/739

CPC分类号： H01L27/0251 ,  H01L27/0266 ,  H01L29/0634 ,  H01L29/1087 ,  H01L29/404 ,  H01L29/42368 ,  H01L29/7817 ,  H01L29/7835 ,  H01L29/7838 ,  H01L29/861

摘要： The present invention provides a high-voltage semiconductor device including a deep well, a first doped region disposed in the deep well, a high-voltage well, a second doped region disposed in the high-voltage well, a first gate structure disposed on the high-voltage well between the second doped region and the first doped region, a doped channel region disposed in the high-voltage region and in contact with the second doped region and the deep well, and a third doped region disposed in the high-voltage well. The high-voltage well has a first conductive type, and the deep well, the first doped region, the second doped region, the doped channel region, and the third doped region have a second conductive type different from the first conductive type.

摘要翻译： 本发明提供了一种高压半导体器件，包括深阱，设置在深阱中的第一掺杂区，高电压阱，设置在高压阱中的第二掺杂区，设置在高阱上的第一栅极结构 在所述第二掺杂区域和所述第一掺杂区域之间的高电压阱，设置在所述高压区域中并与所述第二掺杂区域和所述深阱接触的掺杂沟道区域，以及设置在所述高压区域中的第三掺杂区域 好。 高电压阱具有第一导电类型，并且深阱，第一掺杂区域，第二掺杂区域，掺杂沟道区域和第三掺杂区域具有不同于第一导电类型的第二导电类型。

公开(公告)号：US20130187225A1

公开(公告)日：2013-07-25

申请号：US13354439

申请日：2012-01-20

申请人： Chih-Chung WANG ,  Ming-Tsung Lee ,  Chung-I Huang ,  Shan-Shi Huang ,  Wen-Fang Lee ,  Te-Yuan Wu

发明人： Chih-Chung WANG ,  Ming-Tsung Lee ,  Chung-I Huang ,  Shan-Shi Huang ,  Wen-Fang Lee ,  Te-Yuan Wu

IPC分类号： H01L29/78

CPC分类号： H01L29/0878 ,  H01L21/266 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/402 ,  H01L29/404 ,  H01L29/66681 ,  H01L29/7816

摘要： A HV MOSFET device includes a substrate, a deep well region, a source/body region, a drain region, a gate structure, and a first doped region. The deep well region includes a boundary site and a middle site. The source/body region is formed in the deep well region and defines a channel region. The first doped region is formed in the deep well region and disposed under the gate structure, and having the first conductivity type. There is a first ratio between a dopant dose of the first doped region and a dopant dose of the boundary site of the deep well region. There is a second ratio between a dopant dose of the first doped region and a dopant dose of the middle site of the deep well region. A percentage difference between the first ratio and the second ratio is smaller than or equal to 5%.

摘要翻译： HV MOSFET器件包括衬底，深阱区，源极/主体区，漏极区，栅极结构和第一掺杂区。 深井区域包括边界站点和中间站点。 源/体区域形成在深阱区域中并且限定沟道区域。 第一掺杂区域形成在深阱区域中并且设置在栅极结构下方并且具有第一导电类型。 在第一掺杂区域的掺杂剂剂量和深阱区域的边界位点的掺杂剂剂量之间存在第一比率。 在第一掺杂区域的掺杂剂剂量和深井区域的中间位点的掺杂剂剂量之间存在第二比率。 第一比率和第二比率之间的百分比差小于或等于5％。

公开(公告)号：US08492835B1

公开(公告)日：2013-07-23

申请号：US13354439

申请日：2012-01-20

申请人： Chih-Chung Wang ,  Ming-Tsung Lee ,  Chung-I Huang ,  Shan-Shi Huang ,  Wen-Fang Lee ,  Te-Yuan Wu

发明人： Chih-Chung Wang ,  Ming-Tsung Lee ,  Chung-I Huang ,  Shan-Shi Huang ,  Wen-Fang Lee ,  Te-Yuan Wu

IPC分类号： H01L29/76 ,  H01L29/94

CPC分类号： H01L29/0878 ,  H01L21/266 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/402 ,  H01L29/404 ,  H01L29/66681 ,  H01L29/7816

摘要： A HV MOSFET device includes a substrate, a deep well region, a source/body region, a drain region, a gate structure, and a first doped region. The deep well region includes a boundary site and a middle site. The source/body region is formed in the deep well region and defines a channel region. The first doped region is formed in the deep well region and disposed under the gate structure, and having the first conductivity type. There is a first ratio between a dopant dose of the first doped region and a dopant dose of the boundary site of the deep well region. There is a second ratio between a dopant dose of the first doped region and a dopant dose of the middle site of the deep well region. A percentage difference between the first ratio and the second ratio is smaller than or equal to 5%.

摘要翻译： HV MOSFET器件包括衬底，深阱区，源极/主体区，漏极区，栅极结构和第一掺杂区。 深井区域包括边界站点和中间站点。 源/体区域形成在深阱区域中并且限定沟道区域。 第一掺杂区域形成在深阱区域中并且设置在栅极结构下方并且具有第一导电类型。 在第一掺杂区域的掺杂剂剂量和深阱区域的边界位点的掺杂剂剂量之间存在第一比率。 在第一掺杂区域的掺杂剂剂量和深井区域的中间位点的掺杂剂剂量之间存在第二比率。 第一比率和第二比率之间的百分比差小于或等于5％。

公开(公告)号：US08890144B2

公开(公告)日：2014-11-18

申请号：US13414723

申请日：2012-03-08

申请人： Pao-An Chang ,  Ching-Ming Lee ,  Te-Yuan Wu ,  Chih-Chung Wang ,  Wen-Fang Lee ,  Wei-Lun Hsu

发明人： Pao-An Chang ,  Ching-Ming Lee ,  Te-Yuan Wu ,  Chih-Chung Wang ,  Wen-Fang Lee ,  Wei-Lun Hsu

IPC分类号： H01L29/04 ,  H01L29/10 ,  H01L31/00

CPC分类号： H01L27/0629 ,  H01L29/0634

摘要： A high voltage semiconductor device includes a substrate, an insulating layer positioned on the substrate, and a silicon layer positioned on the insulating layer. The silicon layer further includes at least a first doped strip, two terminal doped regions formed respectively at two opposite ends of the silicon layer and electrically connected to the first doped strip, and a plurality of second doped strips. The first doped strip and the terminal doped regions include a first conductivity type, the second doped strips include a second conductivity type, and the first conductivity type and the second conductivity type are complementary. The first doped strip and the second doped strips are alternately arranged.

摘要翻译： 高电压半导体器件包括衬底，位于衬底上的绝缘层和位于绝缘层上的硅层。 硅层还包括至少第一掺杂条，分别在硅层的两个相对端形成并电连接到第一掺杂条的两个端子掺杂区和多个第二掺杂条。 第一掺杂带和端子掺杂区包括第一导电类型，第二掺杂条包括第二导电类型，第一导电类型和第二导电类型是互补的。 交替布置第一掺杂条和第二掺杂条。

公开(公告)号：US20130234141A1

公开(公告)日：2013-09-12

申请号：US13414723

申请日：2012-03-08

申请人： Pao-An Chang ,  Ching-Ming Lee ,  Te-Yuan Wu ,  Chih-Chung Wang ,  Wen-Fang Lee ,  Wei-Lun Hsu

发明人： Pao-An Chang ,  Ching-Ming Lee ,  Te-Yuan Wu ,  Chih-Chung Wang ,  Wen-Fang Lee ,  Wei-Lun Hsu

IPC分类号： H01L27/088

CPC分类号： H01L27/0629 ,  H01L29/0634

摘要： A high voltage semiconductor device includes a substrate, an insulating layer positioned on the substrate, and a silicon layer positioned on the insulating layer. The silicon layer further includes at least a first doped strip, two terminal doped regions formed respectively at two opposite ends of the silicon layer and electrically connected to the first doped strip, and a plurality of second doped strips. The first doped strip and the terminal doped regions include a first conductivity type, the second doped strips include a second conductivity type, and the first conductivity type and the second conductivity type are complementary. The first doped strip and the second doped strips are alternately arranged.

摘要翻译： 高电压半导体器件包括衬底，位于衬底上的绝缘层和位于绝缘层上的硅层。 硅层还包括至少第一掺杂条，分别在硅层的两个相对端形成并电连接到第一掺杂条的两个端子掺杂区和多个第二掺杂条。 第一掺杂带和端子掺杂区包括第一导电类型，第二掺杂条包括第二导电类型，第一导电类型和第二导电类型是互补的。 交替布置第一掺杂条和第二掺杂条。

公开(公告)号：US09105493B2

公开(公告)日：2015-08-11

申请号：US13476019

申请日：2012-05-21

申请人： Ming-Tsung Lee ,  Cheng-Hua Yang ,  Wen-Fang Lee ,  Chih-Chung Wang ,  Te-Yuan Wu

发明人： Ming-Tsung Lee ,  Cheng-Hua Yang ,  Wen-Fang Lee ,  Chih-Chung Wang ,  Te-Yuan Wu

IPC分类号： H01L29/78 ,  H01L29/08 ,  H01L29/06 ,  H01L29/40 ,  H01L29/423

CPC分类号： H01L29/0878 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/404 ,  H01L29/42368 ,  H01L29/7816

摘要： A layout pattern of a high voltage metal-oxide-semiconductor transistor device includes a first doped region having a first conductivity type, a second doped region having the first conductivity type, and an non-continuous doped region formed in between the first doped region and the second doped region. The non-continuous doped region further includes a plurality of third doped regions, a plurality of gaps, and a plurality of fourth doped regions. The gaps and the third doped regions s are alternately arranged, and the fourth doped regions are formed in the gaps. The third doped regions include a second conductivity type complementary to the first conductivity type, and the fourth doped regions include the first conductivity type.

摘要翻译： 高电压金属氧化物半导体晶体管器件的布局图案包括具有第一导电类型的第一掺杂区域，具有第一导电类型的第二掺杂区域和形成在第一掺杂区域和第二掺杂区域之间的非连续掺杂区域 第二掺杂区域。 非连续掺杂区还包括多个第三掺杂区，多个间隙和多个第四掺杂区。 间隙和第三掺杂区域交替排列，并且第四掺杂区域形成在间隙中。 第三掺杂区域包括与第一导电类型互补的第二导电类型，并且第四掺杂区域包括第一导电类型。

公开(公告)号：US20130307071A1

公开(公告)日：2013-11-21

申请号：US13476019

申请日：2012-05-21

申请人： Ming-Tsung Lee ,  Cheng-Hua Yang ,  Wen-Fang Lee ,  Chih-Chung Wang ,  Te-Yuan Wu

发明人： Ming-Tsung Lee ,  Cheng-Hua Yang ,  Wen-Fang Lee ,  Chih-Chung Wang ,  Te-Yuan Wu

IPC分类号： H01L29/78

CPC分类号： H01L29/0878 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/404 ,  H01L29/42368 ,  H01L29/7816

摘要： A layout pattern of a high voltage metal-oxide-semiconductor transistor device includes a first doped region having a first conductivity type, a second doped region having the first conductivity type, and an non-continuous doped region formed in between the first doped region and the second doped region. The non-continuous doped region further includes a plurality of third doped regions, a plurality of gaps, and a plurality of fourth doped regions. The gaps and the third doped regions s are alternately arranged, and the fourth doped regions are formed in the gaps. The third doped regions include a second conductivity type complementary to the first conductivity type, and the fourth doped regions include the first conductivity type.

摘要翻译： 高电压金属氧化物半导体晶体管器件的布局图案包括具有第一导电类型的第一掺杂区域，具有第一导电类型的第二掺杂区域和形成在第一掺杂区域和第二掺杂区域之间的非连续掺杂区域 第二掺杂区域。 非连续掺杂区还包括多个第三掺杂区，多个间隙和多个第四掺杂区。 间隙和第三掺杂区域交替排列，并且第四掺杂区域形成在间隙中。 第三掺杂区域包括与第一导电类型互补的第二导电类型，并且第四掺杂区域包括第一导电类型。