公开(公告)号：US08890144B2

公开(公告)日：2014-11-18

申请号：US13414723

申请日：2012-03-08

申请人： Pao-An Chang ,  Ching-Ming Lee ,  Te-Yuan Wu ,  Chih-Chung Wang ,  Wen-Fang Lee ,  Wei-Lun Hsu

发明人： Pao-An Chang ,  Ching-Ming Lee ,  Te-Yuan Wu ,  Chih-Chung Wang ,  Wen-Fang Lee ,  Wei-Lun Hsu

IPC分类号： H01L29/04 ,  H01L29/10 ,  H01L31/00

CPC分类号： H01L27/0629 ,  H01L29/0634

摘要： A high voltage semiconductor device includes a substrate, an insulating layer positioned on the substrate, and a silicon layer positioned on the insulating layer. The silicon layer further includes at least a first doped strip, two terminal doped regions formed respectively at two opposite ends of the silicon layer and electrically connected to the first doped strip, and a plurality of second doped strips. The first doped strip and the terminal doped regions include a first conductivity type, the second doped strips include a second conductivity type, and the first conductivity type and the second conductivity type are complementary. The first doped strip and the second doped strips are alternately arranged.

摘要翻译： 高电压半导体器件包括衬底，位于衬底上的绝缘层和位于绝缘层上的硅层。 硅层还包括至少第一掺杂条，分别在硅层的两个相对端形成并电连接到第一掺杂条的两个端子掺杂区和多个第二掺杂条。 第一掺杂带和端子掺杂区包括第一导电类型，第二掺杂条包括第二导电类型，第一导电类型和第二导电类型是互补的。 交替布置第一掺杂条和第二掺杂条。

公开(公告)号：US20130234141A1

公开(公告)日：2013-09-12

申请号：US13414723

申请日：2012-03-08

申请人： Pao-An Chang ,  Ching-Ming Lee ,  Te-Yuan Wu ,  Chih-Chung Wang ,  Wen-Fang Lee ,  Wei-Lun Hsu

发明人： Pao-An Chang ,  Ching-Ming Lee ,  Te-Yuan Wu ,  Chih-Chung Wang ,  Wen-Fang Lee ,  Wei-Lun Hsu

IPC分类号： H01L27/088

CPC分类号： H01L27/0629 ,  H01L29/0634

摘要： A high voltage semiconductor device includes a substrate, an insulating layer positioned on the substrate, and a silicon layer positioned on the insulating layer. The silicon layer further includes at least a first doped strip, two terminal doped regions formed respectively at two opposite ends of the silicon layer and electrically connected to the first doped strip, and a plurality of second doped strips. The first doped strip and the terminal doped regions include a first conductivity type, the second doped strips include a second conductivity type, and the first conductivity type and the second conductivity type are complementary. The first doped strip and the second doped strips are alternately arranged.

摘要翻译： 高电压半导体器件包括衬底，位于衬底上的绝缘层和位于绝缘层上的硅层。 硅层还包括至少第一掺杂条，分别在硅层的两个相对端形成并电连接到第一掺杂条的两个端子掺杂区和多个第二掺杂条。 第一掺杂带和端子掺杂区包括第一导电类型，第二掺杂条包括第二导电类型，第一导电类型和第二导电类型是互补的。 交替布置第一掺杂条和第二掺杂条。

公开(公告)号：US08698247B2

公开(公告)日：2014-04-15

申请号：US13156352

申请日：2011-06-09

申请人： Chih-Chung Wang ,  Wei-Lun Hsu ,  Te-Yuan Wu ,  Wen-Fang Lee ,  Ke-Feng Lin ,  Shan-Shi Huang ,  Ming-Tsung Lee

发明人： Chih-Chung Wang ,  Wei-Lun Hsu ,  Te-Yuan Wu ,  Wen-Fang Lee ,  Ke-Feng Lin ,  Shan-Shi Huang ,  Ming-Tsung Lee

IPC分类号： H01L23/62

CPC分类号： H01L27/0277 ,  H01L21/761 ,  H01L21/823481 ,  H01L21/823493 ,  H01L27/0623 ,  H01L27/0922

摘要： The present invention provides a semiconductor device including a substrate, a deep well, a high-voltage well, and a doped region. The substrate and the high-voltage well have a first conductive type, and the deep well and the doped region have a second conductive type different from the first conductive type. The substrate has a high-voltage region and a low-voltage region, and the deep well is disposed in the substrate in the high-voltage region. The high-voltage well is disposed in the substrate between the high-voltage region and the low-voltage region, and the doped region is disposed in the high-voltage well. The doped region and the high-voltage well are electrically connected to a ground.

摘要翻译： 本发明提供一种包括衬底，深阱，高压阱和掺杂区的半导体器件。 衬底和高压阱具有第一导电类型，并且深阱和掺杂区具有不同于第一导电类型的第二导电类型。 衬底具有高电压区域和低电压区域，并且深阱设置在高压区域中的衬底中。 高电压阱设置在高电压区域和低电压区域之间的衬底中，掺杂区域设置在高压阱中。 掺杂区和高电压阱电连接到地。

公开(公告)号：US20120313175A1

公开(公告)日：2012-12-13

申请号：US13156352

申请日：2011-06-09

申请人： Chih-Chung Wang ,  Wei-Lun Hsu ,  Te-Yuan Wu ,  Wen-Fang Lee ,  Ke-Feng Lin ,  Shan-Shi Huang ,  Ming-Tsung Lee

发明人： Chih-Chung Wang ,  Wei-Lun Hsu ,  Te-Yuan Wu ,  Wen-Fang Lee ,  Ke-Feng Lin ,  Shan-Shi Huang ,  Ming-Tsung Lee

IPC分类号： H01L27/06

CPC分类号： H01L27/0277 ,  H01L21/761 ,  H01L21/823481 ,  H01L21/823493 ,  H01L27/0623 ,  H01L27/0922

摘要： The present invention provides a semiconductor device including a substrate, a deep well, a high-voltage well, and a doped region. The substrate and the high-voltage well have a first conductive type, and the deep well and the doped region have a second conductive type different from the first conductive type. The substrate has a high-voltage region and a low-voltage region, and the deep well is disposed in the substrate in the high-voltage region. The high-voltage well is disposed in the substrate between the high-voltage region and the low-voltage region, and the doped region is disposed in the high-voltage well. The doped region and the high-voltage well are electrically connected to a ground.

摘要翻译： 本发明提供一种包括衬底，深阱，高压阱和掺杂区的半导体器件。 衬底和高压阱具有第一导电类型，并且深阱和掺杂区具有不同于第一导电类型的第二导电类型。 衬底具有高电压区域和低电压区域，并且深阱设置在高压区域中的衬底中。 高电压阱设置在高电压区域和低电压区域之间的衬底中，掺杂区域设置在高压阱中。 掺杂区和高电压阱电连接到地。

公开(公告)号：US08436418B2

公开(公告)日：2013-05-07

申请号：US13163734

申请日：2011-06-20

申请人： Chih-Chung Wang ,  Wei-Lun Hsu ,  Te-Yuan Wu ,  Ke-Feng Lin ,  Shan-Shi Huang ,  Ming-Tsung Lee ,  Wen-Fang Lee

发明人： Chih-Chung Wang ,  Wei-Lun Hsu ,  Te-Yuan Wu ,  Ke-Feng Lin ,  Shan-Shi Huang ,  Ming-Tsung Lee ,  Wen-Fang Lee

IPC分类号： H01L29/94

CPC分类号： H01L27/0251 ,  H01L27/0266 ,  H01L29/0634 ,  H01L29/1087 ,  H01L29/404 ,  H01L29/42368 ,  H01L29/7817 ,  H01L29/7835 ,  H01L29/7838 ,  H01L29/861

摘要： The present invention provides a high-voltage semiconductor device including a deep well, a first doped region disposed in the deep well, a high-voltage well, a second doped region disposed in the high-voltage well, a first gate structure disposed on the high-voltage well between the second doped region and the first doped region, a doped channel region disposed in the high-voltage region and in contact with the second doped region and the deep well, and a third doped region disposed in the high-voltage well. The high-voltage well has a first conductive type, and the deep well, the first doped region, the second doped region, the doped channel region, and the third doped region have a second conductive type different from the first conductive type.

摘要翻译： 本发明提供了一种高压半导体器件，包括深阱，设置在深阱中的第一掺杂区，高电压阱，设置在高压阱中的第二掺杂区，设置在高阱上的第一栅极结构 在所述第二掺杂区域和所述第一掺杂区域之间的高电压阱，设置在所述高压区域中并与所述第二掺杂区域和所述深阱接触的掺杂沟道区域，以及设置在所述高压区域中的第三掺杂区域 好。 高电压阱具有第一导电类型，并且深阱，第一掺杂区域，第二掺杂区域，掺杂沟道区域和第三掺杂区域具有不同于第一导电类型的第二导电类型。

公开(公告)号：US20120319189A1

公开(公告)日：2012-12-20

申请号：US13163734

申请日：2011-06-20

申请人： Chih-Chung Wang ,  Wei-Lun Hsu ,  Te-Yuan Wu ,  Ke-Feng Lin ,  Shan-Shi Huang ,  Ming-Tsung Lee ,  Wen-Fang Lee

发明人： Chih-Chung Wang ,  Wei-Lun Hsu ,  Te-Yuan Wu ,  Ke-Feng Lin ,  Shan-Shi Huang ,  Ming-Tsung Lee ,  Wen-Fang Lee

IPC分类号： H01L29/739

CPC分类号： H01L27/0251 ,  H01L27/0266 ,  H01L29/0634 ,  H01L29/1087 ,  H01L29/404 ,  H01L29/42368 ,  H01L29/7817 ,  H01L29/7835 ,  H01L29/7838 ,  H01L29/861

摘要： The present invention provides a high-voltage semiconductor device including a deep well, a first doped region disposed in the deep well, a high-voltage well, a second doped region disposed in the high-voltage well, a first gate structure disposed on the high-voltage well between the second doped region and the first doped region, a doped channel region disposed in the high-voltage region and in contact with the second doped region and the deep well, and a third doped region disposed in the high-voltage well. The high-voltage well has a first conductive type, and the deep well, the first doped region, the second doped region, the doped channel region, and the third doped region have a second conductive type different from the first conductive type.

摘要翻译： 本发明提供了一种高压半导体器件，包括深阱，设置在深阱中的第一掺杂区，高电压阱，设置在高压阱中的第二掺杂区，设置在高阱上的第一栅极结构 在所述第二掺杂区域和所述第一掺杂区域之间的高电压阱，设置在所述高压区域中并与所述第二掺杂区域和所述深阱接触的掺杂沟道区域，以及设置在所述高压区域中的第三掺杂区域 好。 高电压阱具有第一导电类型，并且深阱，第一掺杂区域，第二掺杂区域，掺杂沟道区域和第三掺杂区域具有不同于第一导电类型的第二导电类型。

公开(公告)号：US08921937B2

公开(公告)日：2014-12-30

申请号：US13216276

申请日：2011-08-24

申请人： Chih-Chung Wang ,  Wei-Lun Hsu ,  Shan-Shi Huang ,  Ke-Feng Lin ,  Te-Yuan Wu

发明人： Chih-Chung Wang ,  Wei-Lun Hsu ,  Shan-Shi Huang ,  Ke-Feng Lin ,  Te-Yuan Wu

IPC分类号： H01L29/78 ,  H01L21/336 ,  H01L29/08 ,  H01L21/266 ,  H01L29/66 ,  H01L29/06 ,  H01L29/40 ,  H01L29/423

CPC分类号： H01L29/66681 ,  H01L21/0334 ,  H01L21/266 ,  H01L29/0619 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/402 ,  H01L29/404 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/66659 ,  H01L29/7816

摘要： The present invention provides a high voltage metal-oxide-semiconductor transistor device including a substrate, a deep well, and a doped region. The substrate and the doped region have a first conductive type, and the substrate has at least one electric field concentration region. The deep well has a second conductive type different from the first conductive type. The deep well is disposed in the substrate, and the doped region is disposed in the deep well. The doping concentrations of the doped region and the deep well in the electric field have a first ratio, and the doping concentrations of the doped region and the deep well outside the electric field have a second ratio. The first ratio is greater than the second ratio.

摘要翻译： 本发明提供一种包括衬底，深阱和掺杂区的高电压金属氧化物半导体晶体管器件。 衬底和掺杂区域具有第一导电类型，并且衬底具有至少一个电场集中区域。 深井具有不同于第一导电类型的第二导电类型。 深阱设置在衬底中，并且掺杂区域设置在深阱中。 掺杂区域和深阱在电场中的掺杂浓度具有第一比例，并且掺杂区域和电场外的深阱的掺杂浓度具有第二比例。 第一比例大于第二比率。

公开(公告)号：US20130049114A1

公开(公告)日：2013-02-28

申请号：US13216276

申请日：2011-08-24

申请人： Chih-Chung Wang ,  Wei-Lun Hsu ,  Shan-Shi Huang ,  Ke-Feng Lin ,  Te-Yuan Wu

发明人： Chih-Chung Wang ,  Wei-Lun Hsu ,  Shan-Shi Huang ,  Ke-Feng Lin ,  Te-Yuan Wu

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/66681 ,  H01L21/0334 ,  H01L21/266 ,  H01L29/0619 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/402 ,  H01L29/404 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/66659 ,  H01L29/7816

摘要： The present invention provides a high voltage metal-oxide-semiconductor transistor device including a substrate, a deep well, and a doped region. The substrate and the doped region have a first conductive type, and the substrate has at least one electric field concentration region. The deep well has a second conductive type different from the first conductive type. The deep well is disposed in the substrate, and the doped region is disposed in the deep well. The doping concentrations of the doped region and the deep well in the electric field have a first ratio, and the doping concentrations of the doped region and the deep well outside the electric field have a second ratio. The first ratio is greater than the second ratio.

摘要翻译： 本发明提供一种包括衬底，深阱和掺杂区的高电压金属氧化物半导体晶体管器件。 衬底和掺杂区域具有第一导电类型，并且衬底具有至少一个电场集中区域。 深井具有不同于第一导电类型的第二导电类型。 深阱设置在衬底中，并且掺杂区域设置在深阱中。 掺杂区域和深阱在电场中的掺杂浓度具有第一比例，并且掺杂区域和电场外的深阱的掺杂浓度具有第二比例。 第一比例大于第二比率。

公开(公告)号：US20120038414A1

公开(公告)日：2012-02-16

申请号：US13282482

申请日：2011-10-27

申请人： Sung-Nien Tang ,  Wei-Lun Hsu ,  Ching-Ming Lee ,  Te-Yuan Wu

发明人： Sung-Nien Tang ,  Wei-Lun Hsu ,  Ching-Ming Lee ,  Te-Yuan Wu

IPC分类号： G05F3/02

CPC分类号： H01L27/085 ,  H01L29/7817 ,  H03F3/195

摘要： A method for operating a semiconductor device including a lateral double diffused metal oxide semiconductor (LDMOS) with a first source, a common drain and a first gate, a junction field effect transistor (JFET) with a second source, the common drain and a second gate wherein the second source is electrically connected to the first gate and an inner circuit electrically connected to the first source is provided. The first source provides the inner circuit with an inner current to generate an inner voltage by means of the lateral double diffused metal oxide semiconductor, and the lateral double diffused metal oxide semiconductor turns off when the inner voltage is elevated substantially as high as the first gate voltage.

摘要翻译： 一种用于操作包括具有第一源极，公共漏极和第一栅极的横向双扩散金属氧化物半导体（LDMOS）的半导体器件的方法，具有第二源极的结型场效应晶体管（JFET），所述公共漏极和第二源极 栅极，其中第二源极电连接到第一栅极，并且提供与第一源电连接的内部电路。 第一源为内部电路提供内部电流，以通过横向双扩散金属氧化物半导体产生内部电压，并且当内部电压升高到与第一栅极高相同时，横向双扩散金属氧化物半导体截止 电压。

公开(公告)号：US08072011B2

公开(公告)日：2011-12-06

申请号：US12573884

申请日：2009-10-06

申请人： Sung-Nien Tang ,  Wei-Lun Hsu ,  Ching-Ming Lee ,  Te-Yuan Wu

发明人： Sung-Nien Tang ,  Wei-Lun Hsu ,  Ching-Ming Lee ,  Te-Yuan Wu

IPC分类号： H01L29/80 ,  H01L31/112

CPC分类号： H01L27/085 ,  H01L29/7817 ,  H03F3/195

摘要： A semiconductor device includes a lateral double diffused metal oxide semiconductor (LDMOS) , a junction field effect transistor (JFET) and an inner circuit. The lateral double diffused metal oxide semiconductor includes a first source, a common drain and a first gate. The junction field effect transistor includes a second source, the common drain and a second gate. The second source is electrically connected to the first gate. The inner circuit is electrically connected to the first source.

摘要翻译： 半导体器件包括横向双扩散金属氧化物半导体（LDMOS），结型场效应晶体管（JFET）和内部电路。 横向双扩散金属氧化物半导体包括第一源极，公共漏极和第一栅极。 结型场效应晶体管包括第二源极，公共漏极和第二栅极。 第二源电连接到第一栅极。 内部电路电连接到第一源。