公开(公告)号：US20060277379A1

公开(公告)日：2006-12-07

申请号：US11414554

申请日：2006-05-01

申请人： Fabien Funfrock ,  Jochen Kallscheuer ,  Michael Sommer ,  Christian Stocken

发明人： Fabien Funfrock ,  Jochen Kallscheuer ,  Michael Sommer ,  Christian Stocken

IPC分类号： G06F12/14 ,  G06F12/00

CPC分类号： G11C7/1045 ,  G11C7/20 ,  G11C8/12 ,  G11C11/4072 ,  G11C11/408

摘要： An integrated semiconductor memory device includes a first memory zone, a second memory zone, first address connections and a second address connection. A second address signal present at the second address connection specifies the access to the first or second memory zone, whereas it is specified via first address signals at the first address connections which memory cell is accessed within the first or second memory zone. In a first memory configuration, all address connections are driven externally with address signals and the access to a memory cell in the first or second memory zone is controlled. In a second memory configuration, only the first address connections are driven externally whereas a signaling bit in a mode register regulates the access to the first or second memory zone. This provides for access to the second memory zone even if there is no possibility of externally driving the second address connection.

摘要翻译： 集成半导体存储器件包括第一存储区，第二存储区，第一地址连接和第二地址连接。 存在于第二地址连接处的第二地址信号指定对第一或第二存储器区域的访问，而通过第一地址连接处的第一地址信号指定在第一或第二存储器区域内访问哪个存储器单元。 在第一存储器配置中，所有地址连接由地址信号从外部驱动，并且控制对第一或第二存储器区域中的存储器单元的访问。 在第二存储器配置中，仅第一地址连接从外部驱动，而模式寄存器中的信令位调节对第一或第二存储器区的访问。 即使不存在外部驱动第二地址连接的可能性，也可以访问第二存储区域。

公开(公告)号：US20050138506A1

公开(公告)日：2005-06-23

申请号：US10949935

申请日：2004-09-24

申请人： Christian Stocken ,  Michael Sommer

发明人： Christian Stocken ,  Michael Sommer

IPC分类号： G11C29/56 ,  G11C5/00 ,  G01R31/28

CPC分类号： G11C29/56 ,  G11C2029/0407 ,  G11C2029/5602

摘要： An apparatus (1) for testing a memory module (2) suitable for exchanging electrical signals with a motherboard (10) contains a device (8a-8k) suitable for detecting the operating state of at least one semiconductor chip (26a-26m) of the module, which device comprises a first set of signal lines (8a-8k), a microcontroller (3) with a memory device (32) for storing the operating state, said microcontroller being electrically connected to the signal lines (8a-8k), a clock generator (5) suitable for generating an operating clock, said clock generator being electrically connected to the microcontroller (3), and a signal connection (13) suitable for communicating a signal for controlling access to the memory module (2) between the circuit board arrangement (10) and the microcontroller (3) and for communicating to the microcontroller (3) a signal for initiating a process of detecting the operating state.

摘要翻译： 一种用于测试适合于与主板（10）交换电信号的存储模块（2）的装置（1），其包含适于检测至少一个半导体芯片（26a- 26m），该装置包括第一组信号线（8a-8k），具有用于存储操作状态的存储器件（32）的微控制器（3），所述微控制器电连接到信号 线路（8a-8k），适于产生工作时钟的时钟发生器（5），所述时钟发生器电连接到微控制器（3），以及信号连接（13），适于传送用于控制访问的信号 到电路板装置（10）和微控制器（3）之间的存储器模块（2）并且用于与微控制器（3）通信用于启动检测操作状态的过程的信号。

公开(公告)号：US09646710B2

公开(公告)日：2017-05-09

申请号：US13558287

申请日：2012-07-25

申请人： Michael Sommer

发明人： Michael Sommer

IPC分类号： G11C17/00 ,  G11C17/10 ,  H01L27/112

CPC分类号： G11C17/10 ,  H01L27/112 ,  H01L27/11226 ,  Y10T29/49002

摘要： Embodiments relate to a semiconductor device, including a channel area; a gate line extending along the channel area so that the channel area can be set into a conductive state by activating the gate line; a plurality of terminals including an electrical connection to the channel area, so that the plurality of terminals is connectable to a predetermined voltage by activating the gate line.

公开(公告)号：US09133963B2

公开(公告)日：2015-09-15

申请号：US13101294

申请日：2011-05-05

申请人： Helmut Geppert ,  Frank Schmidt ,  Michael Sommer

发明人： Helmut Geppert ,  Frank Schmidt ,  Michael Sommer

IPC分类号： F16L3/08 ,  F16L3/12 ,  F16L3/123

CPC分类号： F16L3/12 ,  F16L3/1233

摘要： A clamp for securing a tubular or hose-shaped object on a support. The clamp includes a clamp jacket having first and second ends, wherein a first leg protrudes from the first end of the clamp jacket and a second leg projects from the second end of the clamp jacket. The first leg has a lug which in the open state protrudes in the direction of the second leg. The second leg includes a fastening section which can be inserted into a gap between the lug and a neighboring portion of the first leg located opposite the lug, wherein, in the closed state of the clamp, the lug is plastically deformed toward the outer side of the fastening section facing away from the first leg.

摘要翻译： 用于将管状或软管形物体固定在支撑件上的夹具。 夹具包括具有第一和第二端的夹套，其中第一腿从夹套的第一端伸出，并且第二腿从夹套的第二端伸出。 第一腿具有在第二腿的方向上处于打开状态的凸耳。 第二腿部包括紧固部分，该紧固部分可以插入到凸耳与位于凸耳相对的第一腿部的相邻部分之间的间隙中，其中，在夹紧件的关闭状态下，凸耳朝向外部侧面塑性变形 紧固部分背离第一腿部。

公开(公告)号：US08125821B2

公开(公告)日：2012-02-28

申请号：US11756639

申请日：2007-06-01

申请人： Jan Otterstedt ,  Thomas Nirschl ,  Christian Peters ,  Michael Bollu ,  Wolf Allers ,  Michael Sommer

发明人： Jan Otterstedt ,  Thomas Nirschl ,  Christian Peters ,  Michael Bollu ,  Wolf Allers ,  Michael Sommer

IPC分类号： G11C11/00

CPC分类号： G11C13/004 ,  G11C11/56 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0069 ,  G11C2013/0071 ,  G11C2013/0073 ,  G11C2013/0078 ,  G11C2213/15 ,  G11C2213/79

摘要： One or more embodiments are related to a method of operating a phase-change memory array, including: providing the phase-change memory array, the phase-change memory array including a phase-change memory element in series with an access device between a first address line and a power line; causing a first current through the memory element from the first address line to the power line; and causing a second current through the memory element from the power line to the first address line.

摘要翻译： 一个或多个实施例涉及一种操作相变存储器阵列的方法，包括：提供相变存储器阵列，所述相变存储器阵列包括与存取装置串联的相变存储器元件，位于第一 地址线和电力线; 引起从第一地址线到电力线的存储元件的第一电流; 并且引起从电力线到第一地址线的存储元件的第二电流。

公开(公告)号：US20090316463A1

公开(公告)日：2009-12-24

申请号：US12143577

申请日：2008-06-20

申请人： Michael Sommer

发明人： Michael Sommer

IPC分类号： G11C17/00 ,  H01S4/00 ,  H01L29/76

CPC分类号： G11C17/10 ,  H01L27/112 ,  H01L27/11226 ,  Y10T29/49002

摘要： Embodiments relate to a semiconductor device, including a channel area; a gate line extending along the channel area so that the channel area can be set into a conductive state by activating the gate line; a plurality of terminals including an electrical connection to the channel area, so that the plurality of terminals is connectable to a predetermined voltage by activating the gate line.

摘要翻译： 实施例涉及包括通道区域的半导体器件; 沿着沟道区延伸的栅极线，使得可以通过激活栅极线将沟道区域设置为导通状态; 多个终端，其包括与所述通道区域的电连接，使得通过激活所述栅极线，所述多个端子可连接到预定电压。

公开(公告)号：US07582701B2

公开(公告)日：2009-09-01

申请号：US11368070

申请日：2006-03-03

申请人： Bernd Goebelt ,  Gerard Reestman ,  Karlheinz Haubennestel ,  Barbel Gertzen ,  Michael Sommer

发明人： Bernd Goebelt ,  Gerard Reestman ,  Karlheinz Haubennestel ,  Barbel Gertzen ,  Michael Sommer

IPC分类号： C08L53/00 ,  C08L67/00

CPC分类号： C08L67/06 ,  C08F293/005 ,  C08K3/013 ,  C08K7/02 ,  C08L53/00 ,  C08L101/025 ,  C08L2205/00 ,  C08L2666/14 ,  C08L2666/04 ,  C08L2666/02 ,  C08L2666/24

摘要： The invention relates to an unsaturated polyester resin mixture which can be cured by applying external pressure and which encompasses at least the following components: a) an unsaturated polyester resin whose weight-average molar mass is from 500 to 5000 g/mol; b) an ethylenically unsaturated monomer; c) a shrinkage-reducing component; d) an inert filler; and e) a reinforcing fibre; and f) from 0.01 to 1% by weight of a block copolymer, based on the total weight of the unsaturated polyester resin mixture comprising reinforcing fibre, where the block copolymer encompasses at least one A block and encompasses at least one B block, where the A block contains at least one amine-containing, ethylenically unsaturated monomer; and the B block contains at least one alkyl- and/or phenyl-containing, ethylenically unsaturated monomer, and is free from amine-containing, ethylenically unsaturated monomers. The present invention further relates to a process for preparation of the polyester resin mixtures and to the use of the block copolymers f) in unsaturated polyester resin mixtures.

摘要翻译： 本发明涉及一种不饱和聚酯树脂混合物，其可以通过施加外部压力固化，并且至少包含以下组分：a）重均摩尔质量为500至5000g / mol的不饱和聚酯树脂; b）烯属不饱和单体; c）减缩组分; d）惰性填料; 和e）增强纤维; 和f）0.01至1重量％的嵌段共聚物，基于包含增强纤维的不饱和聚酯树脂混合物的总重量，其中嵌段共聚物包含至少一个A嵌段并且包含至少一个B嵌段，其中 嵌段含有至少一种含胺的烯属不饱和单体; 并且B嵌段含有至少一种含烷基和/或苯基的烯属不饱和单体，并且不含胺的烯属不饱和单体。 本发明还涉及一种制备聚酯树脂混合物的方法，以及在不饱和聚酯树脂混合物中使用嵌段共聚物f）。

公开(公告)号：US07376018B2

公开(公告)日：2008-05-20

申请号：US11416085

申请日：2006-05-01

申请人： Michael Sommer

发明人： Michael Sommer

IPC分类号： G11C11/34

CPC分类号： G11C16/0416

摘要： A non-volatile memory device includes a plurality of word lines, a plurality of sense lines, and a plurality of non-volatile memory cells. Each memory cell includes a floating gate transistor having a control gate, a floating gate separated dielectrically from the control gate, a drain connection and a source connection. The control gate is connected to one of the word lines and the source connection is connected to one of the sense lines, the drain connection being electrically isolated from the other memory cells. A method for reading the memory device and a method for operating the memory device are also provided.

摘要翻译： 非易失性存储器件包括多个字线，多个感测线和多个非易失性存储器单元。 每个存储单元包括具有控制栅极的浮动栅极晶体管，从控制栅极电介质分离的浮动栅极，漏极连接和源极连接。 控制栅极连接到字线之一，源极连接到感测线之一，漏极连接与其它存储单元电隔离。 还提供了一种用于读取存储器件的方法和用于操作存储器件的方法。

公开(公告)号：US20080056024A1

公开(公告)日：2008-03-06

申请号：US11846914

申请日：2007-08-29

申请人： Michael Bollu ,  Michael Sommer

发明人： Michael Bollu ,  Michael Sommer

IPC分类号： G11C7/00

CPC分类号： G11C7/062 ,  G11C7/1051 ,  G11C7/1069 ,  G11C16/26 ,  G11C2207/063

摘要： A device for reading out memory information storable in a memory has an integrator and a comparator. The memory provides, in a hold phase, a leakage current, and in a readout phase, a readout current. The readout current is dependent on the stored memory information. The integrator is adapted to integrate a quantity derived from the leakage current during the hold phase, and to provide a leakage voltage corresponding to an integrated leakage current. The integrator is further adapted to integrate a quantity derived from the readout current during the readout phase, and to provide a readout voltage corresponding to an integrated readout current. The comparator may compare the leakage voltage to the readout voltage and provide, in dependence on the comparison, a readout value corresponding to the memory information.

摘要翻译： 用于读出存储在存储器中的存储器信息的装置具有积分器和比较器。 存储器在保持阶段提供泄漏电流，并且在读出阶段提供读出电流。 读出电流取决于存储的存储器信息。 积分器适于在保持阶段期间积分从泄漏电流导出的量，并提供与集成的泄漏电流相对应的泄漏电压。 积分器进一步适于在读出阶段期间积分从读出电流导出的量，并提供对应于积分读出电流的读出电压。 比较器可以将泄漏电压与读出电压进行比较，并根据比较提供对应于存储器信息的读出值。

公开(公告)号：US07335936B2

公开(公告)日：2008-02-26

申请号：US10744051

申请日：2003-12-23

申请人： Michael Sommer ,  Gerhard Enders

发明人： Michael Sommer ,  Gerhard Enders

IPC分类号： H01L29/72

CPC分类号： H01L27/10864 ,  H01L27/10841 ,  H01L27/10891 ,  H01L29/66181

摘要： Memory cell having a trench capacitor that is constructed in a lower region of a substantially perpendicular trench hole, and which comprises an inner and an outer electrode, a dielectric layer being arranged between the inner and the outer electrodes, a vertical selection transistor that has a substantially perpendicular channel region, which is constructed adjacent to an upper region of the trench hole and which connects the inner electrode of the trench capacitor to a bit line, it being possible to construct a conductive channel as a function of the potential of a word line in the channel region, the channel region partially enclosing the trench hole in its upper region, and the associated work line at least partially surrounding the channel region.

摘要翻译： 具有沟槽电容器的存储单元，其构造在基本上垂直的沟槽孔的下部区域中，并且包括内部和外部电极，布置在内部和外部电极之间的电介质层，垂直选择晶体管，其具有 基本上垂直的沟道区域，其被构造成与沟槽孔的上部区域相邻并且将沟槽电容器的内部电极连接到位线，可以构造作为字线的电位的函数的导电沟道 在通道区域中，通道区域部分地围绕其上部区域中的沟槽孔，并且相关联的工作线至少部分地围绕通道区域。