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    Method for guaranteeing program correctness using fine-grained hardware speculative execution
    4.
    发明授权
    Method for guaranteeing program correctness using fine-grained hardware speculative execution 有权
    使用细粒度硬件推测执行来保证程序正确性的方法

    公开(公告)号：US09195550B2

    公开(公告)日：2015-11-24

    申请号：US13020228

    申请日：2011-02-03

    申请人： Dan Tsafrir ,  Robert W. Wisniewski

    发明人： Dan Tsafrir ,  Robert W. Wisniewski

    IPC分类号： G06F11/08 ,  G06F11/14 ,  G06F9/38 ,  G06F12/08 ,  G06F9/46 ,  G06F9/52

    CPC分类号： G06F11/1489 ,  G06F9/3851 ,  G06F9/466 ,  G06F9/467 ,  G06F9/528 ,  G06F12/0842 ,  G06F12/0846

    摘要： A method for checking program correctness may include executing a program on a main hardware thread in speculative execution mode on a hardware execution context on a chip having a plurality of hardware execution contexts. In this mode, the main hardware thread's state is not committed to main memory. Correctness checks by a plurality of helper threads are executed in parallel to the main hardware thread. Each helper thread runs on a separate hardware execution context on the chip in parallel with the main hardware thread. The correctness checks determine a safe point in the program up to which the operations executed by the main hardware thread are correct. Once the main hardware thread reaches the safe point, the mode of execution of the main hardware thread is switched to non-speculative. The runtime then causes the main thread to re-enter speculative mode of execution.

    摘要翻译： 用于检查程序正确性的方法可以包括在具有多个硬件执行上下文的芯片上的硬件执行上下文上以推测执行模式在主硬件线程上执行程序。 在这种模式下，主硬件线程的状态不会被提供给主内存。 多个辅助线程的正确性检查与主硬件线程并行执行。 每个辅助线程与主要硬件线程并行运行在芯片上的单独硬件执行环境上。 正确性检查确定程序中的安全点，主要硬件线程执行的操作是正确的。 一旦主要硬件线程到达安全点，主硬件线程的执行模式切换为非投机模式。 然后运行时使主线程重新输入推测的执行模式。

    Method to utilize cores in different operating system partitions
    6.
    发明授权
    Method to utilize cores in different operating system partitions 有权
    在不同操作系统分区中使用内核的方法

    公开(公告)号：US08918799B2

    公开(公告)日：2014-12-23

    申请号：US13435100

    申请日：2012-03-30

    申请人： Todd A. Inglett ,  Yoonho Park ,  Bryan S. Rosenburg ,  Robert W. Wisniewski

    发明人： Todd A. Inglett ,  Yoonho Park ,  Bryan S. Rosenburg ,  Robert W. Wisniewski

    IPC分类号： G06F3/00 ,  G06F9/44 ,  G06F9/46 ,  G06F13/00

    CPC分类号： G06F9/545 ,  G06F9/5077 ,  Y02D10/22 ,  Y02D10/36

    摘要： A system call utility may be provided on a first operating system managing a first hardware computing entity. The system call utility may take as an argument a pointer to a computer code a second operating system established to run on the first hardware computing entity. The first operating system is enabled to execute the computer code natively on the first hardware computing entity, and return a result of the computer code executed on the first hardware computing entity to the second operating system.

    摘要翻译： 可以在管理第一硬件计算实体的第一操作系统上提供系统调用实用程序。 系统调用实用程序可以将建立为在第一硬件计算实体上运行的第二操作系统的指针作为计算机代码的指针。 第一操作系统能够在第一硬件计算实体上本地执行计算机代码，并将在第一硬件计算实体上执行的计算机代码的结果返回给第二操作系统。

    Using DMA for copying performance counter data to memory
    7.
    发明授权
    Using DMA for copying performance counter data to memory 失效
    使用DMA将性能计数器数据复制到存储器

    公开(公告)号：US08621167B2

    公开(公告)日：2013-12-31

    申请号：US13446467

    申请日：2012-04-13

    申请人： Alan Gara ,  Valentina Salapura ,  Robert W. Wisniewski

    发明人： Alan Gara ,  Valentina Salapura ,  Robert W. Wisniewski

    IPC分类号： G06F12/00

    CPC分类号： G06F13/28 ,  G06F11/34 ,  G06F2201/88

    摘要： A device for copying performance counter data includes hardware path that connects a direct memory access (DMA) unit to a plurality of hardware performance counters and a memory device. Software prepares an injection packet for the DMA unit to perform copying, while the software can perform other tasks. In one aspect, the software that prepares the injection packet runs on a processing core other than the core that gathers the hardware performance counter data.

    摘要翻译： 用于复制性能计数器数据的设备包括将直接存储器访问（DMA）单元连接到多个硬件性能计数器和存储器设备的硬件路径。 软件为DMA单元准备一个注入数据包来执行复制，而软件可以执行其他任务。 在一个方面，准备注射分组的软件在收集硬件性能计数器数据的核心以外的处理核上运行。

    MECHANISM FOR OPTIMIZED INTRA-DIE INTER-NODELET MESSAGING COMMUNICATION
    8.
    发明申请
    MECHANISM FOR OPTIMIZED INTRA-DIE INTER-NODELET MESSAGING COMMUNICATION 有权
    优化内部信号通信通信机制

    公开(公告)号：US20130326180A1

    公开(公告)日：2013-12-05

    申请号：US13485074

    申请日：2012-05-31

    申请人： Amith R. Mamidala ,  Valentina Salapura ,  Robert W. Wisniewski

    发明人： Amith R. Mamidala ,  Valentina Salapura ,  Robert W. Wisniewski

    IPC分类号： G06F12/14

    CPC分类号： G06F9/544 ,  G06F15/167

    摘要： Point-to-point intra-nodelet messaging support for nodelets on a single chip that obey MPI semantics may be provided. In one aspect, a local buffering mechanism is employed that obeys standard communication protocols for the network communications between the nodelets integrated in a single chip. Sending messages from one nodelet to another nodelet on the same chip may be performed not via the network, but by exchanging messages in the point-to-point messaging buckets between the nodelets. The messaging buckets need not be part of the memory system of the nodelets. Specialized hardware controllers may be used for moving data between the nodelets and each messaging bucket, and ensuring correct operation of the network protocol.

    摘要翻译： 可以提供在遵循MPI语义的单个芯片上的节点的点对点节点内消息支持。 在一个方面，采用本地缓冲机制，其遵循集成在单个芯片中的节点之间的网络通信的标准通信协议。 从同一芯片上的一个节点发送消息到另一个节点可能不是通过网络执行的，而是通过在节点之间的点对点消息存储区中交换消息。 消息传递桶不需要是节点的内存系统的一部分。 专用硬件控制器可用于在节点和每个消息传送桶之间移动数据，并确保网络协议的正确操作。

    METHOD FOR GUARANTEEING PROGRAM CORRECTNESS USING FINE-GRAINED HARDWARE SPECULATIVE EXECUTION
    9.
    发明申请
    METHOD FOR GUARANTEEING PROGRAM CORRECTNESS USING FINE-GRAINED HARDWARE SPECULATIVE EXECUTION 有权
    使用细粒度分布式执行程序保证程序正确性的方法

    公开(公告)号：US20120204065A1

    公开(公告)日：2012-08-09

    申请号：US13020228

    申请日：2011-02-03

    申请人： Dan Tsafrir ,  Robert W. Wisniewski

    发明人： Dan Tsafrir ,  Robert W. Wisniewski

    IPC分类号： G06F11/36

    CPC分类号： G06F11/1489 ,  G06F9/3851 ,  G06F9/466 ,  G06F9/467 ,  G06F9/528 ,  G06F12/0842 ,  G06F12/0846

    摘要： A method for checking program correctness may include executing a program on a main hardware thread in speculative execution mode on a hardware execution context on a chip having a plurality of hardware execution contexts. In this mode, the main hardware thread's state is not committed to main memory. Correctness checks by a plurality of helper threads are executed in parallel to the main hardware thread. Each helper thread runs on a separate hardware execution context on the chip in parallel with the main hardware thread. The correctness checks determine a safe point in the program up to which the operations executed by said main hardware thread are correct. Once the main hardware thread reaches the safe point, the mode of execution of the main hardware thread is switched to non-speculative. The runtime then causes the main thread to re-enter speculative mode of execution.

    摘要翻译： 用于检查程序正确性的方法可以包括在具有多个硬件执行上下文的芯片上的硬件执行上下文上以推测执行模式在主硬件线程上执行程序。 在这种模式下，主硬件线程的状态不会被提供给主内存。 多个辅助线程的正确性检查与主硬件线程并行执行。 每个辅助线程与主要硬件线程并行运行在芯片上的单独硬件执行环境上。 正确性检查确定程序中的安全点，所述主要硬件线程执行的操作是正确的。 一旦主要硬件线程到达安全点，主硬件线程的执行模式切换为非投机模式。 然后运行时使主线程重新输入推测的执行模式。

    METHOD AND APPARATUS FOR A HIERARCHICAL SYNCHRONIZATION BARRIER IN A MULTI-NODE SYSTEM
    10.
    发明申请
    METHOD AND APPARATUS FOR A HIERARCHICAL SYNCHRONIZATION BARRIER IN A MULTI-NODE SYSTEM 审中-公开
    多节点系统中分层同步障碍的方法与装置

    公开(公告)号：US20120179896A1

    公开(公告)日：2012-07-12

    申请号：US12987523

    申请日：2011-01-10

    申请人： Valentina Salapura ,  Robert W. Wisniewski

    发明人： Valentina Salapura ,  Robert W. Wisniewski

    IPC分类号： G06F9/30

    CPC分类号： G06F9/522 ,  G06F9/30087 ,  G06F9/3851

    摘要： A hierarchical barrier synchronization of cores and nodes on a multiprocessor system, in one aspect, may include providing by each of a plurality of threads on a chip, input bit signal to a respective bit in a register, in response to reaching a barrier; determining whether all of the plurality of threads reached the barrier by electrically tying bits of the register together and “AND”ing the input bit signals; determining whether only on-chip synchronization is needed or whether inter-node synchronization is needed; in response to determining that all of the plurality of threads on the chip reached the barrier, notifying the plurality of threads on the chip, if it is determined that only on-chip synchronization is needed; and after all of the plurality of threads on the chip reached the barrier, communicating the synchronization signal to outside of the chip, if it is determined that inter-node synchronization is needed.

    摘要翻译： 在一个方面，多处理器系统上的核心和节点的层级屏障同步可以包括：响应于达到屏障，将芯片上的多个线程中的每一个提供给寄存器中的相应位的输入比特信号; 确定所有多个线程是否通过将所述寄存器的位电一体化并将所述输入位信号“AND”到达所述障碍物; 确定是否仅需要片上同步或者是否需要节点间同步; 响应于确定芯片上的所有多个线程到达屏障，通知芯片上的多个线程，如果确定仅需要片上同步; 并且如果确定需要节点间同步，则在芯片上的所有多个线程到达屏障之后，将同步信号传送到芯片外部。