公开(公告)号：US11024731B2

公开(公告)日：2021-06-01

申请号：US16171521

申请日：2018-10-26

申请人： Cree, Inc.

发明人： Jason Patrick Henning ,  Qingchun Zhang ,  Sei-Hyung Ryu ,  Anant Kumar Agarwal ,  John Williams Palmour ,  Scott Allen

IPC分类号： H01L29/78 ,  H01L29/739 ,  H01L29/06 ,  H01L21/04 ,  H01L25/18 ,  H01L29/16 ,  H01L27/06 ,  H01L29/66 ,  H01L29/04 ,  H02M7/00 ,  H02P7/03

摘要： A power module is disclosed that includes a housing with an interior chamber wherein multiple switch modules are mounted within the interior chamber. The switch modules comprise multiple transistors and diodes that are interconnected to facilitate switching power to a load. In one embodiment, at least one of the switch modules supports a current density of at least 10 amperes per cm2.

公开(公告)号：US09231122B2

公开(公告)日：2016-01-05

申请号：US14169266

申请日：2014-01-31

申请人： Cree, Inc.

发明人： Jason Patrick Henning ,  Qingchun Zhang ,  Sei-Hyung Ryu ,  Anant Kumar Agarwal ,  John Williams Palmour ,  Scott Allen

IPC分类号： H01L29/15 ,  H01L29/872 ,  H01L29/861 ,  H01L29/06

CPC分类号： H01L29/872 ,  H01L29/0619 ,  H01L29/0661 ,  H01L29/1608 ,  H01L29/8611 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/05567 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2924/00014 ,  H01L2924/12032 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/00 ,  H01L2224/05552

摘要： The present disclosure generally relates to a Schottky diode that has a substrate, a drift layer provided over the substrate, and a Schottky layer provided over an active region of the drift layer. The metal for the Schottky layer and the semiconductor material for the drift layer are selected to provide a low barrier height Schottky junction between the drift layer and the Schottky layer.

摘要翻译： 本公开总体上涉及具有衬底，设置在衬底上的漂移层和设置在漂移层的有源区上的肖特基层的肖特基二极管。 选择用于肖特基金属的金属和用于漂移层的半导体材料以在漂移层和肖特基层之间提供低势垒高度的肖特基结。

公开(公告)号：US10707858B2

公开(公告)日：2020-07-07

申请号：US15980101

申请日：2018-05-15

申请人： Cree, Inc.

发明人： Mrinal K. Das ,  Adam Barkley ,  Brian Fetzer ,  Jonathan Young ,  Van Mieczkowski ,  Scott Allen

IPC分类号： H01L29/76 ,  H01L29/94 ,  H03K17/10 ,  H02M7/00 ,  H02M3/158 ,  H01L23/31 ,  H01L29/16 ,  H01L29/78 ,  H03K17/12 ,  H03K17/74 ,  H01L23/00 ,  H01L23/373 ,  H01L23/482 ,  H01L23/528 ,  H01L23/532 ,  H01L29/872 ,  H01L25/11 ,  H01L29/06 ,  H01L25/07 ,  H01L29/739

摘要： A power module includes a first terminal, a second terminal, and a number of semiconductor die coupled between the first terminal and the second terminal. The semiconductor die are configured to provide a low-resistance path for current flow from the first terminal to the second terminal during a forward conduction mode of operation and a high-resistance path for current flow from the first terminal to the second terminal during a forward blocking configuration. Due to improvements made to the power module, it is able to pass a temperature, humidity, and bias test at 80% of its rated voltage for at least 1000 hours.

公开(公告)号：US10269955B2

公开(公告)日：2019-04-23

申请号：US15407689

申请日：2017-01-17

申请人： Cree, Inc.

发明人： Sei-Hyung Ryu ,  Marcelo Schupbach ,  Adam Barkley ,  Scott Allen

IPC分类号： H01L29/78 ,  H01L29/16 ,  H01L29/423 ,  H01L29/06 ,  H01L29/739 ,  H01L29/10

摘要： A vertical FET includes a silicon carbide substrate having a top surface and a bottom surface opposite the top surface; a drain/collector contact on the bottom surface of the silicon carbide substrate; and an epitaxial structure on the top surface of the silicon carbide substrate having formed therein a first source/emitter implant. A gate dielectric is provided on a portion of the epitaxial structure. First source/emitter contact segments are spaced apart from each other and on the first source/emitter implant. A first elongated gate contact and a second elongated gate contact are on the gate dielectric and positioned such that the first source/emitter implant is below and between the first elongated gate contact and the second elongated gate contact. Inter-gate plates extend from at least one of the first elongated gate contact and the second elongated gate contact into spaces formed between the first source/emitter contact segments.

公开(公告)号：US20180204945A1

公开(公告)日：2018-07-19

申请号：US15407689

申请日：2017-01-17

申请人： Cree, Inc.

发明人： Sei-Hyung Ryu ,  Marcelo Schupbach ,  Adam Barkley ,  Scott Allen

IPC分类号： H01L29/78 ,  H01L29/16 ,  H01L29/423 ,  H01L29/06 ,  H01L29/739 ,  H01L29/10

CPC分类号： H01L29/7827 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/7395 ,  H01L29/7802

摘要： A vertical FET includes a silicon carbide substrate having a top surface and a bottom surface opposite the top surface; a drain/collector contact on the bottom surface of the silicon carbide substrate; and an epitaxial structure on the top surface of the silicon carbide substrate having formed therein a first source/emitter implant. A gate dielectric is provided on a portion of the epitaxial structure. First source/emitter contact segments are spaced apart from each other and on the first source/emitter implant. A first elongated gate contact and a second elongated gate contact are on the gate dielectric and positioned such that the first source/emitter implant is below and between the first elongated gate contact and the second elongated gate contact. Inter-gate plates extend from at least one of the first elongated gate contact and the second elongated gate contact into spaces formed between the first source/emitter contact segments.

公开(公告)号：US09865750B2

公开(公告)日：2018-01-09

申请号：US14810678

申请日：2015-07-28

申请人： Cree, Inc.

发明人： Jason Patrick Henning ,  Qingchun Zhang ,  Sei-Hyung Ryu ,  Anant Kumar Agarwal ,  John Williams Palmour ,  Scott Allen

IPC分类号： H01L29/872 ,  H01L29/861 ,  H01L29/06

CPC分类号： H01L29/872 ,  H01L29/0619 ,  H01L29/0661 ,  H01L29/1608 ,  H01L29/8611 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/05567 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2924/00014 ,  H01L2924/12032 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/00 ,  H01L2224/05552

摘要： The present disclosure generally relates to a Schottky diode that has a substrate, a drift layer provided over the substrate, and a Schottky layer provided over an active region of the drift layer. The metal for the Schottky layer and the semiconductor material for the drift layer are selected to provide a low barrier height Schottky junction between the drift layer and the Schottky layer.

公开(公告)号：US20180331679A1

公开(公告)日：2018-11-15

申请号：US15980101

申请日：2018-05-15

申请人： Cree, Inc.

发明人： Mrinal K. Das ,  Adam Barkley ,  Brian Fetzer ,  Jonathan Young ,  Van Mieczkowski ,  Scott Allen

IPC分类号： H03K17/10 ,  H03K17/12 ,  H01L29/78 ,  H01L29/16 ,  H01L23/31 ,  H01L23/532 ,  H01L23/528 ,  H01L25/16 ,  H02M3/158 ,  H02M7/00

摘要： A power module includes a first terminal, a second terminal, and a number of semiconductor die coupled between the first terminal and the second terminal. The semiconductor die are configured to provide a low-resistance path for current flow from the first terminal to the second terminal during a forward conduction mode of operation and a high-resistance path for current flow from the first terminal to the second terminal during a forward blocking configuration. Due to improvements made to the power module, it is able to pass a temperature, humidity, and bias test at 80% of its rated voltage for at least 1000 hours.

公开(公告)号：US20170263713A1

公开(公告)日：2017-09-14

申请号：US15482936

申请日：2017-04-10

申请人： Cree, Inc.

发明人： Jason Patrick Henning ,  Qingchun Zhang ,  Sei-Hyung Ryu ,  Anant Kumar Agarwal ,  John Williams Palmour ,  Scott Allen

IPC分类号： H01L29/16 ,  H01L21/04

CPC分类号： H01L29/7805 ,  H01L21/046 ,  H01L21/049 ,  H01L25/18 ,  H01L27/0629 ,  H01L29/045 ,  H01L29/0696 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/7395 ,  H01L29/7802 ,  H01L29/7806 ,  H01L2924/0002 ,  H01L2924/13091 ,  H02M7/003 ,  H02P7/04 ,  H01L2924/00

摘要： A power module is disclosed that includes a housing with an interior chamber wherein multiple switch modules are mounted within the interior chamber. The switch modules comprise multiple transistors and diodes that are interconnected to facilitate switching power to a load. In one embodiment, at least one of the switch modules supports a current density of at least 10 amperes per cm2.

公开(公告)号：US20150333191A1

公开(公告)日：2015-11-19

申请号：US14810678

申请日：2015-07-28

申请人： Cree, Inc.

发明人： Jason Patrick Henning ,  Qingchun Zhang ,  Sei-Hyung Ryu ,  Anant Kumar Agarwal ,  John Williams Palmour ,  Scott Allen

IPC分类号： H01L29/872

CPC分类号： H01L29/872 ,  H01L29/0619 ,  H01L29/0661 ,  H01L29/1608 ,  H01L29/8611 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/05567 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2924/00014 ,  H01L2924/12032 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/00 ,  H01L2224/05552

摘要： The present disclosure generally relates to a Schottky diode that has a substrate, a drift layer provided over the substrate, and a Schottky layer provided over an active region of the drift layer. The metal for the Schottky layer and the semiconductor material for the drift layer are selected to provide a low barrier height Schottky junction between the drift layer and the Schottky layer.

摘要翻译： 本公开总体上涉及具有衬底，设置在衬底上的漂移层和设置在漂移层的有源区上的肖特基层的肖特基二极管。 选择用于肖特基金属的金属和用于漂移层的半导体材料以在漂移层和肖特基层之间提供低势垒高度的肖特基结。

公开(公告)号：US20140145213A1

公开(公告)日：2014-05-29

申请号：US14169266

申请日：2014-01-31

申请人： Cree, Inc.

发明人： Jason Patrick Henning ,  Qingchun Zhang ,  Sei-Hyung Ryu ,  Anant Kumar Agarwal ,  John Williams Palmour ,  Scott Allen

IPC分类号： H01L29/872

CPC分类号： H01L29/872 ,  H01L29/0619 ,  H01L29/0661 ,  H01L29/1608 ,  H01L29/8611 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/05567 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2924/00014 ,  H01L2924/12032 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/00 ,  H01L2224/05552

摘要： The present disclosure generally relates to a Schottky diode that has a substrate, a drift layer provided over the substrate, and a Schottky layer provided over an active region of the drift layer. The metal for the Schottky layer and the semiconductor material for the drift layer are selected to provide a low barrier height Schottky junction between the drift layer and the Schottky layer.

摘要翻译： 本公开总体上涉及具有衬底，设置在衬底上的漂移层和设置在漂移层的有源区上的肖特基层的肖特基二极管。 选择用于肖特基金属的金属和用于漂移层的半导体材料以在漂移层和肖特基层之间提供低势垒高度的肖特基结。