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    Semiconductor manufacturing using disposable test circuitry within scribe lanes
    1.
    发明授权
    Semiconductor manufacturing using disposable test circuitry within scribe lanes 有权

    公开(公告)号：US10553508B2

    公开(公告)日：2020-02-04

    申请号：US14153417

    申请日：2014-01-13

    申请人： Douglas M. Reber ,  Sergio A. Ajuria ,  Phuc M. Nguyen

    发明人： Douglas M. Reber ,  Sergio A. Ajuria ,  Phuc M. Nguyen

    IPC分类号： H01L21/66 ,  H01L21/78 ,  H01L23/00

    摘要： Embodiments are disclosed for semiconductor manufacturing using disposable test circuitry formed within scribe lanes. The manufacturing steps can include forming device circuitry within a semiconductor die and forming test circuitry within a scribe lane. One or more electrical connection route lines are also formed that connect the device circuitry and test circuitry blocks. Further, each die can be connected to a single test circuitry block, or multiple dice can share common test circuitry blocks. After testing, the electrical connection route line(s) are sealed, and the test circuitry is discarded when the device dice are singulated. For certain embodiments, the edge of the devices dice are encapsulated with a protective metal layer, and certain other embodiments include protective sealrings through which the connection route lines pass to enter the dice from the test circuitry blocks within the scribe lanes.

    Method for forming a packaged semiconductor device
    2.
    发明授权
    Method for forming a packaged semiconductor device 有权
    用于形成封装的半导体器件的方法

    公开(公告)号：US09134366B2

    公开(公告)日：2015-09-15

    申请号：US14011160

    申请日：2013-08-27

    申请人： Sergio A. Ajuria ,  Phuc M. Nguyen ,  Douglas M. Reber

    发明人： Sergio A. Ajuria ,  Phuc M. Nguyen ,  Douglas M. Reber

    IPC分类号： H01L21/66 ,  G01R31/28 ,  H01L23/522

    CPC分类号： G01R31/2884 ,  G01R31/2896 ,  H01L22/32 ,  H01L23/5226 ,  H01L24/19 ,  H01L2224/13

    摘要： A method of fabricating a packaged semiconductor device includes integrating a plurality of singulated semiconductor die in a die carrier, and forming one or more interconnect layers on the die carrier. The interconnect layers include at least one of conductive intra-layer structures and inter-layer structures coupled to contact pads on the plurality of singulated semiconductor die. A set of landing pads is formed coupled to a first subset of the contact pads via a first set of the conductive intra-layer structures and inter-layer structures. A set of probe pads is formed coupled to a second subset of the contact pads via a second set of the conductive intra-layer structures and inter-layer structures. The die carrier is singulated to form a plurality of packaged semiconductor devices. The set of probe pads is removed during the singulating the die carrier.

    摘要翻译： 制造封装半导体器件的方法包括将多个单片化半导体管芯集成在管芯载体中，并在管芯载体上形成一个或多个互连层。 互连层包括耦合到多个单片半导体管芯上的接触焊盘的导电层内结构和层间结构中的至少一个。 一组着陆焊盘通过第一组导电层内结构和层间结构形成为耦合到接触焊盘的第一子集。 通过第二组导电层内结构和层间结构，形成耦合到接触焊盘的第二子集的一组探针焊盘。 将管芯载体分离以形成多个封装的半导体器件。 在分离模具载体期间移除探针焊盘组。

    Semiconductor Manufacturing Using Disposable Test Circuitry Within Scribe Lanes
    4.
    发明申请
    Semiconductor Manufacturing Using Disposable Test Circuitry Within Scribe Lanes 审中-公开
    半导体制造在标定车道内使用一次性测试电路

    公开(公告)号：US20150200146A1

    公开(公告)日：2015-07-16

    申请号：US14153417

    申请日：2014-01-13

    申请人： Douglas M. Reber ,  Sergio A. Ajuria ,  Phuc M. Nguyen

    发明人： Douglas M. Reber ,  Sergio A. Ajuria ,  Phuc M. Nguyen

    IPC分类号： H01L21/66 ,  H01L23/00 ,  H01L23/29 ,  H01L23/10 ,  H01L21/78

    CPC分类号： H01L22/34 ,  H01L21/78 ,  H01L22/32 ,  H01L23/562 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Embodiments are disclosed for semiconductor manufacturing using disposable test circuitry formed within scribe lanes. The manufacturing steps can include forming device circuitry within a semiconductor die and forming test circuitry within a scribe lane. One or more electrical connection route lines are also formed that connect the device circuitry and test circuitry blocks. Further, each die can be connected to a single test circuitry block, or multiple dice can share common test circuitry blocks. After testing, the electrical connection route line(s) are sealed, and the test circuitry is discarded when the device dice are singulated. For certain embodiments, the edge of the devices dice are encapsulated with a protective metal layer, and certain other embodiments include protective sealrings through which the connection route lines pass to enter the dice from the test circuitry blocks within the scribe lanes.

    摘要翻译： 公开了使用在划线中形成的一次性测试电路的半导体制造的实施例。 制造步骤可以包括在半导体管芯内形成器件电路并在划线内形成测试电路。 还形成一个或多个连接设备电路和测试电路块的电连接路线。 此外，每个管芯可以连接到单个测试电路块，或者多个管芯可以共享公共测试电路块。 测试后，电气连接路线被密封，并且当设备裸片被切割时，测试电路被丢弃。 对于某些实施例，器件裸片的边缘被保护金属层封装，并且某些其它实施例包括保护性密封件，连接路线经过该保护密封件从划线中的测试电路块进入骰子。

    METHOD FOR FORMING A PACKAGED SEMICONDUCTOR DEVICE
    6.
    发明申请
    METHOD FOR FORMING A PACKAGED SEMICONDUCTOR DEVICE 有权
    形成包装半导体器件的方法

    公开(公告)号：US20150061709A1

    公开(公告)日：2015-03-05

    申请号：US14011160

    申请日：2013-08-27

    申请人： Sergio A. Ajuria ,  Phuc M. Nguyen ,  Douglas M. Reber

    发明人： Sergio A. Ajuria ,  Phuc M. Nguyen ,  Douglas M. Reber

    IPC分类号： G01R31/28

    CPC分类号： G01R31/2884 ,  G01R31/2896 ,  H01L22/32 ,  H01L23/5226 ,  H01L24/19 ,  H01L2224/13

    摘要： A method of fabricating a packaged semiconductor device includes integrating a plurality of singulated semiconductor die in a die carrier, and forming one or more interconnect layers on the die carrier. The interconnect layers include at least one of conductive intra-layer structures and inter-layer structures coupled to contact pads on the plurality of singulated semiconductor die. A set of landing pads is formed coupled to a first subset of the contact pads via a first set of the conductive intra-layer structures and inter-layer structures. A set of probe pads is formed coupled to a second subset of the contact pads via a second set of the conductive intra-layer structures and inter-layer structures. The die carrier is singulated to form a plurality of packaged semiconductor devices. The set of probe pads is removed during the singulating the die carrier.

    摘要翻译： 制造封装半导体器件的方法包括将多个单片化半导体管芯集成在管芯载体中，并在管芯载体上形成一个或多个互连层。 互连层包括耦合到多个单片半导体管芯上的接触焊盘的导电层内结构和层间结构中的至少一个。 一组着陆焊盘通过第一组导电层内结构和层间结构形成为耦合到接触焊盘的第一子集。 通过第二组导电层内结构和层间结构，形成耦合到接触焊盘的第二子集的一组探针焊盘。 将管芯载体分离以形成多个封装的半导体器件。 在分离模具载体期间移除探针焊盘组。