公开(公告)号：US20160064294A1

公开(公告)日：2016-03-03

申请号：US14470383

申请日：2014-08-27

申请人： DOUGLAS M. REBER ,  Sergio A. Ajuria ,  Phuc M. Nguyen

发明人： DOUGLAS M. REBER ,  Sergio A. Ajuria ,  Phuc M. Nguyen

IPC分类号： H01L21/66 ,  H01L21/48 ,  H01L23/00

CPC分类号： H01L21/4846 ,  H01L22/34 ,  H01L23/522 ,  H01L23/562 ,  H01L23/585 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/81 ,  H01L24/85 ,  H01L24/92 ,  H01L24/94 ,  H01L2224/02311 ,  H01L2224/0237 ,  H01L2224/02371 ,  H01L2224/0239 ,  H01L2224/039 ,  H01L2224/0392 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05023 ,  H01L2224/05548 ,  H01L2224/05568 ,  H01L2224/05572 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/1146 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/81203 ,  H01L2224/85048 ,  H01L2224/85205 ,  H01L2224/85207 ,  H01L2224/8581 ,  H01L2224/92 ,  H01L2224/9212 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/3512 ,  H01L2924/35121 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/00012 ,  H01L2224/0231 ,  H01L2224/03 ,  H01L2924/014 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

摘要： An integrated circuit die includes a first bond pad having a bond contact area at a first depth into a plurality of build-up layers over a semiconductor substrate of the integrated circuit die, having sidewalls that surround the bond contact area, the sidewalls extending from the first depth to a top surface of the plurality of build-up layers, and having a top portion that extends over a portion of a top surface of the plurality of build-up layers.

摘要翻译： 集成电路管芯包括第一接合焊盘，该第一接合焊盘在集成电路管芯的半导体衬底上的第一深度处具有多个堆叠层中的接合区域，其具有包围接合区域的侧壁， 第一深度到多个堆积层的顶表面，并且具有在多个堆积层的顶表面的一部分上延伸的顶部。

公开(公告)号：US20120299190A1

公开(公告)日：2012-11-29

申请号：US13114100

申请日：2011-05-24

申请人： DOUGLAS M. REBER ,  Lawrence N. Herr

发明人： DOUGLAS M. REBER ,  Lawrence N. Herr

IPC分类号： H01L23/48 ,  G06F17/50

CPC分类号： H01L21/76816 ,  G06F17/5081

摘要： A method for tiling selected vias in a semiconductor device is provided. The semiconductor device includes a plurality of vias. The method includes: generating a layout database for the semiconductor device; identifying isolated vias of the plurality of vias; selecting the isolated vias; defining a zone around each of the selected isolated vias; and adding tiling features on a metal layer above the selected isolated vias and within the zone. The method improves reliability of the semiconductor device by allowing moisture to vent from around the vias.

摘要翻译： 提供了一种在半导体器件中平铺所选择的通孔的方法。 半导体器件包括多个通孔。 该方法包括：生成用于半导体器件的布局数据库; 识别多个通孔中的隔离通孔; 选择隔离通孔; 在每个所选择的隔离通孔周围限定区域; 以及在所选择的隔离通孔上方和区域内的金属层上添加平铺特征。 该方法通过允许湿气从通孔周围排出来提高半导体器件的可靠性。

公开(公告)号：US20130134595A1

公开(公告)日：2013-05-30

申请号：US13305410

申请日：2011-11-28

申请人： DOUGLAS M. REBER

发明人： DOUGLAS M. REBER

IPC分类号： H01L23/48 ,  G06F17/50

CPC分类号： G06F17/5068 ,  G06F2217/72 ,  H01L21/76814 ,  H01L21/76828 ,  H01L23/5226 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for increasing metal density around selected vias in a semiconductor device is provided. The semiconductor device includes a plurality of vias. The method includes: generating a layout database for the semiconductor device; identifying isolated vias of the plurality of vias; selecting the isolated vias; defining a zone around each of the selected isolated vias; and increasing area of a metal layer which is above the selected isolated via and which encloses the selected isolated via within each zone to achieve a target metal density within the zone. The method improves reliability of the semiconductor device by allowing moisture to vent from around the vias.

摘要翻译： 提供了一种用于在半导体器件中选择的通孔周围增加金属密度的方法。 半导体器件包括多个通孔。 该方法包括：生成用于半导体器件的布局数据库; 识别多个通孔中的隔离通孔; 选择隔离通孔; 在每个所选择的隔离通孔周围限定区域; 并且增加在所选择的隔离通孔上方的金属层的面积，并且在每个区域内包围所选择的隔离通孔，以实现该区域内的目标金属密度。 该方法通过允许水分从通孔周围排出来提高半导体器件的可靠性。

公开(公告)号：US20130105986A1

公开(公告)日：2013-05-02

申请号：US13285073

申请日：2011-10-31

申请人： DOUGLAS M. REBER ,  Mehul D. Shroff ,  Edward O. Travis

发明人： DOUGLAS M. REBER ,  Mehul D. Shroff ,  Edward O. Travis

IPC分类号： H01L23/48 ,  G06F17/50

CPC分类号： G06F13/4027 ,  G06F17/5077 ,  H01L23/5221 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/5286 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device comprises conductive buses and conductive bridges. A respective conductive bridge is conductively coupled to at least two portions of at least one of the conductive buses. At least N plus one (N+1) vias are coupled between every one of the conductive bridges and a respective feature in an integrated circuit when: (1) a width of the respective conductive bridge is less than a width of each of the at least two portions of the at least one of the conductive buses to which the respective conductive bridge is coupled, and (2) a distance along the respective conductive bridge and at least one of the vias is less than a critical distance. N is a number of conductive couplings between the respective one of the conductive bridges and the at least one of the conductive buses.

摘要翻译： 半导体器件包括导电总线和导电桥。 相应的导电桥与至少一个导电总线的至少两个部分导电耦合。 当以下情况下，至少N + 1个（N + 1）通孔耦合在每个导电桥和集成电路中的相应特征之间：（1）相应导电桥的宽度小于每个导体桥的宽度 所述至少一个导电总线的至少一个导体总线的至少两个部分相互连接，并且（2）沿相应导电桥和至少一个通孔的距离小于临界距离。 N是在相应的一个导电桥和至少一个导电总线之间的多个导电耦合。

公开(公告)号：US20140094029A1

公开(公告)日：2014-04-03

申请号：US14096051

申请日：2013-12-04

申请人： DOUGLAS M. REBER ,  Mehul D. Shroff ,  Edward O. Travis

发明人： DOUGLAS M. REBER ,  Mehul D. Shroff ,  Edward O. Travis

IPC分类号： H01L21/768

CPC分类号： H01L21/76877 ,  G06F17/5077 ,  H01L21/4763 ,  H01L21/76816 ,  H01L23/5226 ,  H01L29/401 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method includes forming a connection between a first metal layer and a second metal layer. The second metal layer is over the first metal layer. A via location for a first via between the first metal layer and the second metal layer is identified. Additional locations for first additional vias are determined. The first additional vias are determined to be necessary for stress migration issues. Additional locations necessary for second additional vias are determined. The second additional vias are determined to be necessary for electromigration issues. The first via and the one of the group consisting of (i) the first additional vias and second additional vias (ii) the first additional vias plus a number of vias sufficient for electromigration issues taking into account that the first additional vias, after taking into account the stress migration issues, still have an effective via number greater than zero.

公开(公告)号：US20140091475A1

公开(公告)日：2014-04-03

申请号：US13630996

申请日：2012-09-28

申请人： DOUGLAS M. REBER

发明人： DOUGLAS M. REBER

IPC分类号： G06F17/50 ,  H01L23/48

CPC分类号： G06F17/5068 ,  G06F2217/72 ,  H01L21/76814 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/0001 ,  H01L2924/00

摘要： A semiconductor device comprising a first insulating layer, a first metal conductor layer formed over the first insulating layer, a second insulating layer comprising a low-k insulating material formed over the first metal conductor, a second metal conductor layer formed over the second insulating layer, vias formed in the second insulating layer connecting the first metal conductor layer to the second metal conductor layer, and a plurality of metal lines. One of the metal lines is expanded around one of the vias compared to metal lines around other ones of the vias so that predetermined areas around each of the vias meets a minimum metal density.

摘要翻译： 一种半导体器件，包括第一绝缘层，形成在第一绝缘层上的第一金属导体层，包含形成在第一金属导体上的低k绝缘材料的第二绝缘层，形成在第二绝缘层上的第二金属导体层 形成在连接第一金属导体层和第二金属导体层的第二绝缘层中的通孔，以及多个金属线。 与围绕其他通孔的金属线相比，其中一条金属线扩展到其中一条通孔，使得每个通孔周围的预定区域达到最小金属密度。