公开(公告)号：US06950488B2

公开(公告)日：2005-09-27

申请号：US09945599

申请日：2001-09-04

申请人： Dae-hyun Chung ,  Ho-young Song

发明人： Dae-hyun Chung ,  Ho-young Song

IPC分类号： G11C11/4076 ,  H03H11/26 ,  H03K5/14 ,  H03L7/081 ,  H03L7/089 ,  H04L7/033

CPC分类号： H03L7/089 ,  H03K5/133 ,  H03L7/0814

摘要： Disclosed is a delay locked-loop circuit comprising a phase detector for detecting a phase difference between an external clock signal and an internal clock signal, a delay unit controller for generating a control signal in response to output of the phase detector, and a variable delay unit for delaying the external clock in response to the control signal to synchronize the internal clock with the external clock, the variable delay unit comprising a first group of delay cells used at or above a predetermined frequency, a second group of delay cells used with the first group of delay cells at or below a predetermined frequency, switch transistors for connecting/disconnecting the first group of delay cells and the second group of delay cells to/from a first output line and a second output line of the variable delay unit, respectively, in response to the control signal, and a switch for connecting/disconnecting the first output line to/from the second output line in response to a delay use signal representing the use of one of the delay cells in the first group.

摘要翻译： 公开了一种延迟锁定环电路，包括用于检测外部时钟信号和内部时钟信号之间的相位差的相位检测器，响应于相位检测器的输出产生控制信号的延迟单元控制器，以及可变延迟 单元，用于响应于所述控制信号延迟所述外部时钟以使所述内部时钟与所述外部时钟同步，所述可变延迟单元包括在预定频率以上或以上使用的第一组延迟单元;第二组延迟单元，其与 第一组等于或低于预定频率的延迟单元，分别用于将第一组延迟单元和第二组延迟单元分别连接到可变延迟单元的第一输出线和第二输出线的开关晶体管 响应于控制信号，以及用于响应于延迟而将第一输出线与第二输出线连接/断开的开关 e信号表示使用第一组中的延迟单元之一。

公开(公告)号：US06778464B2

公开(公告)日：2004-08-17

申请号：US10288830

申请日：2002-11-06

申请人： Dae-hyun Chung

发明人： Dae-hyun Chung

IPC分类号： G11C800

CPC分类号： G11C7/1093 ,  G11C7/1039 ,  G11C7/1051 ,  G11C7/1066 ,  G11C7/1072 ,  G11C7/1087

摘要： Synchronous semiconductor memory devices and methods of operating are provided. The device has a latency N and includes a memory cell array, a stack unit having N storage units and a frequency detector that provides an output signal based on the relationship of the frequency of operation clock to a predetermined frequency. A control circuit controls the stack unit in response to the output signal of the frequency detector. The control circuit latches data read from the memory and controls the stack unit so that the latched data is stored from a clock cycle when a read command is sent until an N-th cycle afterwards if the clock frequency is greater than the predetermined frequency and delays the latched data for one cycle and controls the stack unit so that the delayed data is stored from one cycle after the read command is sent until an N+1 cycle afterwards.

摘要翻译： 提供了同步半导体存储器件和操作方法。 该设备具有延迟N，并且包括存储单元阵列，具有N个存储单元的堆叠单元和基于操作时钟频率与预定频率的关系提供输出信号的频率检测器。 控制电路根据频率检测器的输出信号控制堆栈单元。 控制电路锁存从存储器读取的数据并控制堆栈单元，使得当读命令被发送到第N个周期之后，如果时钟频率大于预定频率并且延迟，则从锁存数据存储从时钟周期 一个周期的锁存数据并控制堆栈单元，以便在发送读命令之后从一个周期开始存储延迟的数据，直到N + 1个周期后。

公开(公告)号：US06882580B2

公开(公告)日：2005-04-19

申请号：US10358739

申请日：2003-02-05

申请人： Hyun-wook Lim ,  Dae-hyun Chung

发明人： Hyun-wook Lim ,  Dae-hyun Chung

IPC分类号： G11C7/22 ,  G11C8/00 ,  G11C11/401 ,  G11C11/407 ,  G11C11/4074 ,  G11C11/4076 ,  H03K5/13 ,  H03L7/00 ,  G11C7/00

CPC分类号： G11C7/222 ,  G11C7/22 ,  G11C2207/105

摘要： A memory device includes first and second power supply pads configured to be connected to a power supply. The memory device further includes a data output circuit that receives power via the first power supply pad and outputs data responsive to an internal clock signal, and a delay-locked loop (DLL) circuit that receives power via the second power supply pad independently of the first power supply pad and that generates the internal clock signal responsive to an external clock signal.

摘要翻译： 存储器件包括被配置为连接到电源的第一和第二电源焊盘。 存储器件还包括数据输出电路，其经由第一电源焊盘接收电力并响应于内部时钟信号输出数据;以及延迟锁定环路（DLL）电路，其经由第二电源焊盘独立地接收电力， 第一电源焊盘，并且响应于外部时钟信号产生内部时钟信号。

公开(公告)号：US06327217B1

公开(公告)日：2001-12-04

申请号：US09679784

申请日：2000-10-05

申请人： Dae-hyun Chung

发明人： Dae-hyun Chung

IPC分类号： G11C800

CPC分类号： G11C7/222 ,  G01R31/30 ,  G11C7/1072 ,  G11C7/22

摘要： A variable delay buffer circuit, as might be used in a synchronous DRAM, includes a buffer circuit that receives an input signal and generates an output signal therefrom responsive to an output enable signal. An output enable signal generation circuit receives a latency indicating signal and generates the output enable signal responsive to a command signal with a delay that is based on the latency indicating signal. A latency interval definition circuit receives a clock signal and generates at least one latency interval defining signal that defines at least one latency interval. A latency indication circuit receives the at least one latency interval defining signal and a test signal that is delayed a predetermined delay with respect to the clock signal and generates the latency indicating signal therefrom. Related methods are also discussed.

摘要翻译： 可以在同步DRAM中使用的可变延迟缓冲器电路包括缓冲电路，其接收输入信号并根据输出使能信号产生输出信号。 输出使能信号发生电路接收等待时间指示信号，并响应于基于等待时间指示信号的延迟的命令信号产生输出使能信号。 延迟间隔定义电路接收时钟信号并产生定义至少一个等待时间间隔的至少一个等待时间间隔定义信号。 延迟指示电路接收至少一个等待时间间隔定义信号和相对于时钟信号延迟预定延迟的测试信号，并从其生成等待时间指示信号。 还讨论了相关方法。

公开(公告)号：US06920080B2

公开(公告)日：2005-07-19

申请号：US10702366

申请日：2003-11-06

申请人： Dae-hyun Chung ,  Sang-woong Shin

发明人： Dae-hyun Chung ,  Sang-woong Shin

IPC分类号： G11C11/407 ,  G11C7/10 ,  G11C7/22 ,  G11C11/40 ,  G11C11/4076 ,  G11C11/409 ,  G11C8/00

CPC分类号： G11C7/222 ,  G11C7/1072 ,  G11C7/22 ,  G11C11/4076

摘要： A synchronous semiconductor memory device includes an output control signal generating circuit that generates a data output control signal in response to an internal clock signal, an output control clock signal and a CAS latency signal. The output control signal generating circuit successively shifts read information signals in response to the internal clock signal and the output control clock signal, both source clocks of which are identical, and generates one of the shifted read information signals as an output control signal for indicating a data output period in response to the CAS latency signal. The synchronous semiconductor memory device can synchronize the source clocks of the clock signals used in the output control signal generating circuit thereby reducing the influence of clock jitter.

摘要翻译： 同步半导体存储器件包括响应于内部时钟信号，输出控制时钟信号和CAS等待时间信号产生数据输出控制信号的输出控制信号产生电路。 输出控制信号发生电路响应于两个源时钟相同的内部时钟信号和输出控制时钟信号连续地移位读信息信号，并产生一个移位读信息信号作为输出控制信号， 数据输出周期响应CAS延迟信号。 同步半导体存储器件可以使输出控制信号发生电路中使用的时钟信号的源时钟同步，从而减少时钟抖动的影响。

公开(公告)号：US06380799B1

公开(公告)日：2002-04-30

申请号：US09721130

申请日：2000-11-22

申请人： Dae-hyun Chung ,  Jung-bae Lee

发明人： Dae-hyun Chung ,  Jung-bae Lee

IPC分类号： G05F110

CPC分类号： G05F1/56 ,  G06F1/26 ,  G11C5/14 ,  G11C11/407 ,  G11C11/413 ,  H01L21/822 ,  H01L27/04

摘要： An internal voltage generation circuit is provided which can stably generate an internal supply voltage even if an external supply voltage decreases. The internal voltage generation circuit includes first and second level shifters, a differential amplifier and a driver. The first level shifter is connected to an internal supply voltage terminal and lowers the internal supply voltage to a predetermined voltage level. The second level shifter is connected to a reference voltage terminal and lowers a reference voltage to a predetermined voltage level. The differential amplifier compares the output voltage of the second level shifter with the output voltage of the first level shifter and amplifies the difference between the two output voltages. The driver generates the internal supply voltage in response to the output of the differential amplifier. The first and second level shifters may be source followers that decrease the internal supply voltage and the reference supply voltage, respectively, by a threshold voltage. Accordingly, the internal voltage generation circuit may stably generate the internal supply voltage even if the level of the external supply voltage is lowered, and restores the level of the internal supply voltage to its original level equal to the reference voltage even when the level of the internal supply voltage drops.

摘要翻译： 提供内部电压产生电路，即使外部电源电压降低，也能够稳定地产生内部电源电压。 内部电压产生电路包括第一和第二电平移位器，差分放大器和驱动器。 第一电平移位器连接到内部电源电压端子，并将内部电源电压降低到预定电压电平。 第二电平移位器连接到参考电压端子并将参考电压降低到预定电压电平。 差分放大器将第二电平移位器的输出电压与第一电平移位器的输出电压进行比较，并放大两个输出电压之间的差值。 驱动器响应差分放大器的输出产生内部电源电压。 第一和第二电平移位器可以是分别通过阈值电压将内部电源电压和参考电源电压降低的源极跟随器。 因此，即使外部电源电压的电平降低，内部电压产生电路也可以稳定地产生内部电源电压，并且即使当内部电源电平的电平等于参考电压时也将内部电源电压的电平恢复到其原始电平 内部电源电压下降。

公开(公告)号：US06987407B2

公开(公告)日：2006-01-17

申请号：US10744215

申请日：2003-12-22

申请人： Dae-hyun Chung ,  Sang-woong Shin ,  Woo-jin Lee

发明人： Dae-hyun Chung ,  Sang-woong Shin ,  Woo-jin Lee

IPC分类号： H03L7/06

CPC分类号： G11C7/1066 ,  G11C7/1051 ,  G11C7/222 ,  H03L7/0812

摘要： A delay locked loop (DLL) is provided that includes a phase detector configured to detect a phase error between an internal clock signal and the external clock signal and output a phase error signal. A low pass filter is configured to output a predetermined control signal in response to the phase error signal. A variable delay circuit is configured to change a delay time in response to the predetermined control signal, delay the phase of the external clock signal with respect to the changed delay time, lock the delayed external clock signal and output the internal clock signal. A compensation delay circuit is configured to receive a control voltage based on a delay time introduced by a data output circuit and delay a phase of the internal clock signal for a first delay time based on the control voltage and output the delayed internal clock signal to the phase detector. Methods of compensating a delay for a DLL are also provided.

摘要翻译： 提供了延迟锁定环（DLL），其包括被配置为检测内部时钟信号和外部时钟信号之间的相位误差并输出相位误差信号的相位检测器。 低通滤波器被配置为响应于相位误差信号输出预定的控制信号。 可变延迟电路被配置为响应于预定控制信号改变延迟时间，相对于改变的延迟时间延迟外部时钟信号的相位，锁定延迟的外部时钟信号并输出​​内部时钟信号。 补偿延迟电路被配置为基于由数据输出电路引入的延迟时间接收控制电压，并且基于控制电压延迟内部时钟信号的第一延迟时间的相位，并将延迟的内部时钟信号输出到 相位检测器。 还提供了补偿DLL的延迟的方法。