公开(公告)号：US07652919B2

公开(公告)日：2010-01-26

申请号：US11771961

申请日：2007-06-29

申请人： Darlene G. Hamilton ,  Kulachet Tanpairoj ,  Fatima Bathul ,  Ou Li

发明人： Darlene G. Hamilton ,  Kulachet Tanpairoj ,  Fatima Bathul ,  Ou Li

IPC分类号： G11C11/34

CPC分类号： G11C11/5671 ,  G11C16/0475 ,  G11C16/0491 ,  G11C16/3418 ,  G11C16/3427

摘要： The claimed subject matter provides systems and/or methods that facilitate programming and reading multi-level, multi-bit memory cells in a memory device. In multi-bit memory cells, programming one element can affect the second element. Certain combinations of elements can cause excessive levels of complementary bit disturb, state dependent non-uniform charge loss, and state dependent program disturb, reducing memory device reliability. Such effects may be pronounced where a high charge level is programmed into a first element while a second element of the same memory cell is unprogrammed. Memory cell elements can be programmed using additional charge levels to mitigate such effects. For example, the sixteen distinct element combinations possible using four charge levels can be mapped to a subset of twenty-five possible element combinations using five charge levels, avoiding element combinations likely to generate excessive complementary bit disturb, state dependent non-uniform charge loss, and state dependent program disturb.

摘要翻译： 所要求保护的主题提供了便于在存储器件中编程和读取多级多位存储器单元的系统和/或方法。 在多位存储器单元中，编程一个元件可以影响第二个元件。 元件的某些组合可能导致过多的互补位干扰，状态依赖的不均匀电荷损失和状态相关的程序干扰，从而降低存储器件的可靠性。 当高电荷电平被编程到第一元件中而同一存储器单元的第二元件未被编程时，这种效果可能是显着的。 可以使用额外的电荷电平对存储单元元件进行编程，以减轻这种影响。 例如，使用四个电荷电平可能的十六个不同元件组合可以被映射到使用五个电荷电平的二十五个可能元件组合的子集，避免可能产生过多的互补位干扰，状态依赖的非均匀电荷损失的元件组合， 和状态依赖程序干扰。

公开(公告)号：US20080158954A1

公开(公告)日：2008-07-03

申请号：US11771961

申请日：2007-06-29

申请人： Darlene G. Hamilton ,  Fatima Bathul ,  Kulachet Tanpairoj ,  Ou Li

发明人： Darlene G. Hamilton ,  Fatima Bathul ,  Kulachet Tanpairoj ,  Ou Li

IPC分类号： G11C11/34

CPC分类号： G11C11/5671 ,  G11C16/0475 ,  G11C16/0491 ,  G11C16/3418 ,  G11C16/3427

摘要： The claimed subject matter provides systems and/or methods that facilitate programming and reading multi-level, multi-bit memory cells in a memory device. In multi-bit memory cells, programming one element can affect the second element. Certain combinations of elements can cause excessive levels of complementary bit disturb, state dependent non-uniform charge loss, and state dependent program disturb, reducing memory device reliability. Such effects may be pronounced where a high charge level is programmed into a first element while a second element of the same memory cell is unprogrammed. Memory cell elements can be programmed using additional charge levels to mitigate such effects. For example, the sixteen distinct element combinations possible using four charge levels can be mapped to a subset of twenty-five possible element combinations using five charge levels, avoiding element combinations likely to generate excessive complementary bit disturb, state dependent non-uniform charge loss, and state dependent program disturb.

摘要翻译： 所要求保护的主题提供了便于在存储器件中编程和读取多级多位存储器单元的系统和/或方法。 在多位存储器单元中，编程一个元件可以影响第二个元件。 元件的某些组合可能导致过多的互补位干扰，状态依赖的不均匀电荷损失和状态相关的程序干扰，从而降低存储器件的可靠性。 当高电荷电平被编程到第一元件中而同一存储器单元的第二元件未被编程时，这种效果可能是显着的。 可以使用额外的电荷电平对存储单元元件进行编程，以减轻这种影响。 例如，使用四个电荷电平可能的十六个不同元件组合可以被映射到使用五个电荷电平的二十五个可能的元件组合的子集，避免可能产生过多的互补位干扰，状态依赖的非均匀电荷损失的元件组合， 和状态依赖程序干扰。

公开(公告)号：US20090103357A1

公开(公告)日：2009-04-23

申请号：US11874076

申请日：2007-10-17

申请人： Darlene Hamilton ,  Fatima Bathul ,  Kulachet Tanpairoj ,  Ou Li

发明人： Darlene Hamilton ,  Fatima Bathul ,  Kulachet Tanpairoj ,  Ou Li

IPC分类号： G11C16/10

CPC分类号： G11C16/10 ,  G11C11/5671 ,  G11C16/0475 ,  G11C16/3418 ,  G11C2211/5621

摘要： Methods of rapidly programming a wordline of multi-level flash memory cells comprising memory cell element-pairs having three or more data levels per bit or element corresponding to three or more threshold voltages are provided. An interactive program algorithm rapidly programs the elements of the wordline of memory cells in a learn phase and a single core programming phase. In one embodiment, each wordline comprises learn element-pairs first programmed to provide learn drain voltages for programming core element-pairs along the wordline having the same program pattern of data levels. A set comprising one or more program patterns is chosen to correspond with each program level used on the wordline. The learn element-pairs are programmed to determine a learned program drain voltage for each program level. This learned program drain voltage essentially provides a wordline and program level specific program characterization of the Vd required for the remaining elements of that wordline.

摘要翻译： 提供了快速编程多级闪存单元的字线的方法，其包括每位具有三个或更多个数据级或对应于三个或更多阈值电压的元件的存储单元元件对。 交互式程序算法在学习阶段和单个核心编程阶段快速地对存储器单元的字线的元素进行编程。 在一个实施例中，每个字线包括首先被编程为提供学习漏极电压的学习元件对，用于沿着具有相同数据级别的程序模式的字线编程核心元件对。 选择包括一个或多个节目模式的集合以对应于字线上使用的每个节目级别。 学习元件对被编程以确定每个程序级的学习程序漏极电压。 这个学习的程序漏极电压基本上提供了字线和程序级特定程序表征该字母的剩余元件所需的Vd。

公开(公告)号：US07656705B2

公开(公告)日：2010-02-02

申请号：US11874076

申请日：2007-10-17

申请人： Darlene Hamilton ,  Fatima Bathul ,  Kulachet Tanpairoj ,  Ou Li

发明人： Darlene Hamilton ,  Fatima Bathul ,  Kulachet Tanpairoj ,  Ou Li

IPC分类号： G11C11/34

CPC分类号： G11C16/10 ,  G11C11/5671 ,  G11C16/0475 ,  G11C16/3418 ,  G11C2211/5621

摘要： Methods of rapidly programming a wordline of multi-level flash memory cells comprising memory cell element-pairs having three or more data levels per bit or element corresponding to three or more threshold voltages are provided. An interactive program algorithm rapidly programs the elements of the wordline of memory cells in a learn phase and a single core programming phase. In one embodiment, each wordline comprises learn element-pairs first programmed to provide learn drain voltages for programming core element-pairs along the wordline having the same program pattern of data levels. A set comprising one or more program patterns is chosen to correspond with each program level used on the wordline. The learn element-pairs are programmed to determine a learned program drain voltage for each program level. This learned program drain voltage essentially provides a wordline and program level specific program characterization of the Vd required for the remaining elements of that wordline.

摘要翻译： 提供了快速编程多级闪存单元的字线的方法，其包括每位具有三个或更多个数据级或对应于三个或更多阈值电压的元件的存储单元元件对。 交互式程序算法在学习阶段和单个核心编程阶段快速地对存储器单元的字线的元素进行编程。 在一个实施例中，每个字线包括首先被编程为提供学习漏极电压的学习元件对，用于沿着具有相同数据级别的程序模式的字线编程核心元件对。 选择包括一个或多个节目模式的集合以对应于字线上使用的每个节目级别。 学习元件对被编程以确定每个程序级的学习程序漏极电压。 这个学习的程序漏极电压基本上提供了字线和程序级特定程序表征该字母的剩余元件所需的Vd。

公开(公告)号：US06775187B1

公开(公告)日：2004-08-10

申请号：US10422489

申请日：2003-04-24

申请人： Darlene G. Hamilton ,  Edward F. Runnion ,  Edward Hsia ,  Kulachet Tanpairoj

发明人： Darlene G. Hamilton ,  Edward F. Runnion ,  Edward Hsia ,  Kulachet Tanpairoj

IPC分类号： G11C1604

CPC分类号： G11C16/10 ,  G11C16/0475

摘要： A method of programming a dual cell memory device having a first charge storing cell and second charge storing cell. The first charge storing cell can be pre-read to determine if the first charge storing cell stores an amount of charge to increase a threshold voltage of the memory device over a specified threshold voltage. If not, the second charge storing cell can be programmed with a standard program pulse. If so, the second charge storing cell can be programed with a modified program pulse.

摘要翻译： 一种编程具有第一电荷存储单元和第二电荷存储单元的双单元存储器件的方法。 可以预先读取第一电荷存储单元，以确定第一电荷存储单元是否存储一定量的电荷以增加存储器件的阈值电压超过指定的阈值电压。 如果不是，则可以用标准编程脉冲编程第二电荷存储单元。 如果是这样，则可以用修改的编程脉冲对第二电荷存储单元进行编程。

公开(公告)号：US06590811B1

公开(公告)日：2003-07-08

申请号：US10173262

申请日：2002-06-17

申请人： Darlene G. Hamilton ,  Narbeh Derhacobian ,  Janet S. Y. Wang ,  Kulachet Tanpairoj

发明人： Darlene G. Hamilton ,  Narbeh Derhacobian ,  Janet S. Y. Wang ,  Kulachet Tanpairoj

IPC分类号： G11C1134

CPC分类号： G11C16/3409 ,  G11C11/5671 ,  G11C16/04 ,  G11C16/0475 ,  G11C16/10 ,  G11C16/3404 ,  G11C16/3436 ,  G11C16/3445 ,  G11C16/3459 ,  G11C29/50 ,  G11C29/50004

摘要： A method and system for programming of the normal bits of a memory array of dual bit memory cells is accomplished by programming at a substantially high delta VT. The substantially higher VT assures that the memory array will maintain programmed data and erase data consistently after higher temperature stresses and/or customer operation over substantial periods of time. Furthermore, by utilizing substantially high gate and drain voltages during programming, programming times are kept short without degrading charge loss. A methodology is provided that determines the charge loss for single bit operation during program and erase cycles. The charge losses over cycling and stress are then utilized to determine an appropriate delta VT to be programmed into a command logic and state machine.

公开(公告)号：US06956768B2

公开(公告)日：2005-10-18

申请号：US10413800

申请日：2003-04-15

申请人： Darlene G. Hamilton ,  Kulachet Tanpairoj ,  Edward Hsia ,  Yi He

发明人： Darlene G. Hamilton ,  Kulachet Tanpairoj ,  Edward Hsia ,  Yi He

IPC分类号： G11C11/56 ,  G11C16/04 ,  G11C16/10

CPC分类号： G11C11/5671 ,  G11C16/0475 ,  G11C16/10

摘要： A method of programming a multi-level, dual cell memory device. The method includes independently programming a first charge storing cell and a second charge storing cell to respective data states, the data states selected from a blank program level or one of a plurality of charged program levels. Also disclosed is a method of reading the multi-level, dual cell memory device using a plurality of reference currents.

摘要翻译： 一种编程多级双电池存储器件的方法。 该方法包括将第一电荷存储单元和第二电荷存储单元独立地编程为相应的数据状态，从空白程序级或多个带电程序级中的一个选择的数据状态。 还公开了一种使用多个参考电流读取多电平双电池存储器件的方法。

公开(公告)号：US06822909B1

公开(公告)日：2004-11-23

申请号：US10422090

申请日：2003-04-24

申请人： Darlene G. Hamilton ,  Edward Hsia ,  Mark W. Randolph ,  Edward F. Runnion ,  Kulachet Tanpairoj

发明人： Darlene G. Hamilton ,  Edward Hsia ,  Mark W. Randolph ,  Edward F. Runnion ,  Kulachet Tanpairoj

IPC分类号： G11C1134

CPC分类号： G11C16/0475 ,  G11C11/5671 ,  G11C16/3454

摘要： A method of programming a dual cell memory device having a first charge storing cell and a second charge storing cell. The method can include applying an initial program pulse to the memory device; comparing the threshold voltage of the memory device with a verify threshold voltage; and if the threshold voltage of the memory device is less than the verify threshold voltage, applying a second program pulse to the memory device during which at least one condition of the second program pulse is modified from the initial program pulse.

摘要翻译： 一种编程具有第一电荷存储单元和第二电荷存储单元的双单元存储器件的方法。 该方法可以包括将初始编程脉冲施加到存储器件; 将存储器件的阈值电压与验证阈值电压进行比较; 并且如果所述存储器件的阈值电压小于所述验证​​阈值电压，则向所述存储器件施加第二编程脉冲，在所述存储器件期间，从所述初始编程脉冲修改所述第二编程脉冲的至少一个条件。

公开(公告)号：US06967873B2

公开(公告)日：2005-11-22

申请号：US10677790

申请日：2003-10-02

申请人： Darlene G. Hamilton ,  Zhizheng Liu ,  Mark W. Randolph ,  Yi He ,  Edward Hsia ,  Kulachet Tanpairoj ,  Mimi Lee ,  Alykhan Madhani

发明人： Darlene G. Hamilton ,  Zhizheng Liu ,  Mark W. Randolph ,  Yi He ,  Edward Hsia ,  Kulachet Tanpairoj ,  Mimi Lee ,  Alykhan Madhani

IPC分类号： G11C16/04 ,  G11C16/34 ,  G11C11/34

CPC分类号： G11C16/3404 ,  G11C16/0475 ,  G11C16/107 ,  G11C16/3409 ,  G11C16/344 ,  G11C16/3445 ,  G11C16/345

摘要： A method of erasing a flash electrically erasable read only memory (EEPROM) device composed of a plurality of memory cells includes pre-programming the plurality of memory cells, applying an erase pulse to the plurality of memory cells followed by an erase verification. The erase verification is followed by soft programming any memory cells having a threshold voltage below a predetermined minimum level and applying a positive gate stress to the plurality of memory cells. The erase method prevents overerasing and provides a tightened threshold voltage distribution.

公开(公告)号：US06512701B1

公开(公告)日：2003-01-28

申请号：US09886861

申请日：2001-06-21

申请人： Darlene G. Hamilton ,  Kulachet Tanpairoj ,  Yider Wu

发明人： Darlene G. Hamilton ,  Kulachet Tanpairoj ,  Yider Wu

IPC分类号： G11C1604

CPC分类号： G11C16/16 ,  G11C16/0475 ,  G11C16/0491

摘要： A system and methodology is provided for verifying erasure of one or more dual bit virtual ground memory cells in a memory device, such as a flash memory. Each of the dual bits have a first or normal bit and a second or complimentary bit associated with the first or normal bit. The system and methodology include verifying and erasure of both a normal bit and a complimentary bit of the cell. The erasure includes applying a set of erase pulses to the normal bit and complimentary bit in a single dual bit cell. The set of erase pulses is comprised of a two sided erase pulse to both sides of the bits in the cell or transistor junction followed by a first single sided erase pulse to one side and a second single sided erase pulse to the other side of transistor junction.

摘要翻译： 提供了用于验证擦除存储器设备（例如闪存）中的一个或多个双位虚拟接地存储器单元的系统和方法。 每个双位具有与第一或正常位相关联的第一或正常位和第二或补充位。 系统和方法包括验证和擦除单元的正常位和互补位。 擦除包括将一组擦除脉冲施加到单个双位单元中的正常位和补充位。 该组擦除脉冲由单元或晶体管结中的位的两侧的双侧擦除脉冲组成，之后是一侧的第一单侧擦除脉冲和到晶体管结的另一侧的第二单侧擦除脉冲 。