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    Low defect density composite dielectric
    7.
    发明授权
    Low defect density composite dielectric 失效
    低缺陷密度复合电介质

    公开(公告)号：US5969397A

    公开(公告)日：1999-10-19

    申请号：US974325

    申请日：1997-11-19

    申请人： Douglas Ticknor Grider, III ,  Paul Edward Nicollian ,  Steve Hsia

    发明人： Douglas Ticknor Grider, III ,  Paul Edward Nicollian ,  Steve Hsia

    IPC分类号： H01L29/78 ,  H01L21/28 ,  H01L21/314 ,  H01L21/318 ,  H01L29/51 ,  H01L29/76 ,  H01L29/94

    CPC分类号： H01L21/28185 ,  H01L21/28202 ,  H01L21/3144 ,  H01L29/513 ,  H01L29/518

    摘要： A composite dielectric layer (102). A first layer (112) of the composite dielectric layer (102) has a small to no nitrogen concentration. A second layer (114) of the composite dielectric layer (102) has a larger nitrogen concentration (e.g., 5-15%). The composite dielectric layer (102) may be used as a thin gate dielectric wherein the second layer (114) is located adjacent a doped gate electrode (110) and has sufficient nitrogen concentration to stop penetration of dopant from the gate electrode (110) to the channel region (108). The first layer (112) is located between the second layer (114) and the channel region (108). The low nitrogen concentration of the first layer (112) is limited so as to not interfere with carrier mobility in the channel region (108).

    摘要翻译： 复合电介质层（102）。 复合介电层（102）的第一层（112）具有小至无氮浓度。 复合介电层（102）的第二层（114）具有较大的氮浓度（例如5-15％）。 复合介电层（102）可以用作薄栅极电介质，其中第二层（114）位于掺杂栅电极（110）附近，并且具有足够的氮浓度以阻止掺杂剂从栅电极（110）穿透至 通道区域（108）。 第一层（112）位于第二层（114）和沟道区（108）之间。 限制第一层（112）的低氮浓度，以便不干扰通道区域（108）中的载流子迁移率。

    Method of manufacturing CMOS devices
    8.
    发明授权
    Method of manufacturing CMOS devices 失效
    制造CMOS器件的方法

    公开(公告)号：US4577391A

    公开(公告)日：1986-03-25

    申请号：US635371

    申请日：1984-07-27

    申请人： Steve Hsia ,  Paul Chang

    发明人： Steve Hsia ,  Paul Chang

    IPC分类号： H01L27/092 ,  H01L21/265 ,  H01L21/8238 ,  H01L29/78 ,  H01L21/32

    CPC分类号： H01L21/823864

    摘要： A CMOS semiconductor structure having insulation sidewall spacers whose width is selected independently for NMOS and PMOS devices. The width of the spacer is selected to reduce hot electron injection in the N channel device and to insure that the gate and source regions are aligned with or underlap the gate in the P channel device. A narrower spacer is used for the P channel device than for the N channel device which permits the formation of a P channel device having a threshold voltage less than 1 volt.

    摘要翻译： 具有绝缘侧壁间隔物的CMOS半导体结构，其宽度针对NMOS和PMOS器件独立选择。 选择间隔物的宽度以减少N沟道器件中的热电子注入，并确保栅极和源极区域与P沟道器件中的栅极对准或下划线。 对于P沟道器件使用较窄的间隔物，而不是N沟道器件，其允许形成阈值电压小于1伏特的P沟道器件。

    Self-aligned stack formation
    9.
    发明授权
    Self-aligned stack formation 失效
    自对齐堆叠形成

    公开(公告)号：US06562724B1

    公开(公告)日：2003-05-13

    申请号：US09089795

    申请日：1998-06-03

    申请人： Steve Hsia ,  Yin Hu

    发明人： Steve Hsia ,  Yin Hu

    IPC分类号： H01L21302

    CPC分类号： H01L29/66583 ,  H01L21/28061 ,  H01L21/31116 ,  H01L21/32136 ,  H01L29/4933

    摘要： A method to simplify the polycide gate structure fabrication processes by using a hardmask 240 to define a pattern of siliciding 260 a silicon layer 230, and then using the silicide 260 to mask removal of the unreacted silicon 220 and 230 in locations where the hardmask 240 had been present. The metal silicide 260 formed in the exposed silicon regions 220 and 230 functions as a self-aligned mask against the silicon 220 and 230 etching. By using a selective etching process between the silicon 220 and 230 and the silicide 260, the silicon 220 and 230 can be etched down to the gate oxide 210 to form the polycide (silicide/polysilicon) gate. The polycide gate formed by this method is particularly advantageous in DRAM applications, but can also be used as a MOS gate in a transistor.

    摘要翻译： 一种通过使用硬掩模240来限定硅化层260的图案来硅化硅层230来简化多晶硅栅极结构制造工艺的方法，然后使用硅化物260掩盖在硬掩模240具有的位置处的未反应硅220和230的去除 已经存在 形成在暴露的硅区域220和230中的金属硅化物260用作抵抗硅220和230蚀刻的自对准掩模。 通过在硅220和230与硅化物260之间使用选择性蚀刻工艺，可将硅220和230蚀刻到栅极氧化物210以形成多晶硅化物（硅化物/多晶硅）栅极。 通过该方法形成的多晶硅栅极在DRAM应用中特别有利，但也可以用作晶体管中的MOS栅极。