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58 条记录 (耗时 0.054 秒)

    Wafer clamp ring for use in an ionized physical vapor deposition apparatus
    1.
    发明授权
    Wafer clamp ring for use in an ionized physical vapor deposition apparatus 失效
    用于电离物理气相沉积设备的晶片夹环

    公开(公告)号：US06176931B1

    公开(公告)日：2001-01-23

    申请号：US09430829

    申请日：1999-10-29

    申请人： Darryl D. Restaino ,  Stephen Mark Rossnagel ,  Andrew Herbert Simon ,  Pavel Smetana ,  Edward C. Cooney, III

    发明人： Darryl D. Restaino ,  Stephen Mark Rossnagel ,  Andrew Herbert Simon ,  Pavel Smetana ,  Edward C. Cooney, III

    IPC分类号： C23C1600

    CPC分类号： C23C14/541 ,  C23C14/50

    摘要： Improvements are described for a wafer clamp ring used in an IPVD apparatus to provide cooling for the wafer clamp ring, to protect the wafer clamp ring from ion bombardment, and to prevent damage to the wafer. The wafer clamp ring is placed on a cooling fixture when not required for a deposition process. The fixture is annular in shape and in close thermal contact with a circulating coolant and is thereby cooled below ambient temperature. The cooling line and the cooling fixture are fixed relative to the IPVD device, so that problems associated with flexible cooling lines are avoided. An annular grounded shield may be provided between the plasma and clamp ring to protect the clamp ring against ion bombardment during the deposition process. The wafer clamp ring may have a portion which overhangs the wafer during a deposition process, and which has a ridge portion extending downwards therefrom and tapering to a knife edge. The wafer clamp ring may be fabricated as a split ring with an insulating portion, to prevent heating by induced current in the clamp ring.

    摘要翻译： 描述了用于IPVD装置中的晶片夹环的改进，以为晶片夹环提供冷却，以保护晶片夹环避免离子轰击，并防止损坏晶片。 当不需要沉积工艺时，将晶片夹环放置在冷却夹具上。 固定装置的形状为环形，与循环的冷却剂紧密的热接触，从而被冷却到环境温度以下。 冷却管路和冷却固定装置相对于IPVD装置固定，从而避免与柔性冷却管线相关的问题。 可以在等离子体和夹环之间设置环形接地屏蔽件，以在沉积过程中保护夹环免受离子轰击。 晶片夹环可以具有在沉积工艺期间悬垂于晶片的部分，并且具有从其向下延伸并逐渐变细到刀刃的脊部分。 晶片夹环可以制造成具有绝缘部分的开口环，以防止夹紧环中的感应电流加热。

    Sacrificial metal spacer damascene process
    5.
    发明授权
    Sacrificial metal spacer damascene process 有权
    牺牲金属间隔镶嵌工艺

    公开(公告)号：US07393777B2

    公开(公告)日：2008-07-01

    申请号：US10984439

    申请日：2004-11-09

    申请人： Edward C. Cooney, III ,  Robert M. Geffken ,  Anthony K. Stamper

    发明人： Edward C. Cooney, III ,  Robert M. Geffken ,  Anthony K. Stamper

    IPC分类号： H01L21/4763 ,  H01L21/311

    CPC分类号： H01L21/76844 ,  H01L21/76811 ,  H01L21/76813

    摘要： A method and structure for a dual damascene interconnect structure comprises forming wiring lines in a metallization layer over a substrate, shaping a laminated insulator stack above the metallization layer, patterning a hardmask over the laminated insulator stack, forming troughs in the hardmask, creating sacrificial tungsten sidewall spacers in the troughs, patterning the laminated insulator stack, removing the sacrificial sidewall spacers, forming vias in the patterned laminated insulator stack, and depositing a metal liner and conductive material into the vias and troughs, wherein the laminated insulator stack comprises a dielectric layer further comprising oxide and polyarylene. The step of depositing prevents the laminated insulator stack from sputtering into the vias. Moreover, the step of depositing comprises cleaning the vias and troughs, optionally performing a reactive ion etching or argon sputter cleaning, depositing a plurality of metal layers over the vias and troughs, and depositing copper in the vias and troughs.

    摘要翻译： 用于双镶嵌互连结构的方法和结构包括在衬底上的金属化层中形成布线，在金属化层上方形成叠层绝缘体堆叠，在叠层绝缘体堆叠上形成硬掩模，在硬掩模中形成槽，从而产生牺牲钨 在槽中的侧壁间隔物，图案化叠层绝缘体堆叠，去除牺牲侧壁间隔物，在图案化的层压绝缘体堆叠中形成通孔，以及将金属衬垫和导电材料沉积到通孔和槽中，其中层压绝缘体堆叠包括介电层 还包含氧化物和聚亚芳基。 沉积步骤防止层压的绝缘体叠层溅射到通孔中。 此外，沉积步骤包括清洁通孔和槽，可选地执行反应离子蚀刻或氩溅射清洗，在通孔和槽上沉积多个金属层，以及在通孔和槽中沉积铜。

    Sacrificial metal spacer damascene process
    6.
    发明授权
    Sacrificial metal spacer damascene process 失效
    牺牲金属间隔镶嵌工艺

    公开(公告)号：US06846741B2

    公开(公告)日：2005-01-25

    申请号：US10202134

    申请日：2002-07-24

    申请人： Edward C. Cooney, III ,  Robert M. Geffken ,  Anthony K. Stamper

    发明人： Edward C. Cooney, III ,  Robert M. Geffken ,  Anthony K. Stamper

    IPC分类号： H01L21/768 ,  H01L21/4763

    CPC分类号： H01L21/76844 ,  H01L21/76811 ,  H01L21/76813

    摘要： A method and structure for a dual damascene interconnect structure comprises forming wiring lines in a metallization layer over a substrate, shaping a laminated insulator stack above the metallization layer, patterning a hardmask over the laminated insulator stack, forming troughs in the hardmask, creating sacrificial tungsten sidewall spacers in the troughs, patterning the laminated insulator stack, removing the sacrificial sidewall spacers, forming vias in the patterned laminated insulator stack, and depositing a metal liner and conductive material into the vias and troughs, wherein the laminated insulator stack comprises a dielectric layer further comprising oxide and polyarylene. The step of depositing prevents the laminated insulator stack from sputtering into the vias. Moreover, the step of depositing comprises cleaning the vias and troughs, optionally performing a reactive ion etching or argon sputter cleaning, depositing a plurality of metal layers over the vias and troughs, and depositing copper in the vias and troughs.

    摘要翻译： 用于双镶嵌互连结构的方法和结构包括在衬底上的金属化层中形成布线，在金属化层上方形成叠层绝缘体堆叠，在叠层绝缘体堆叠上形成硬掩模，在硬掩模中形成槽，从而产生牺牲钨 在槽中的侧壁间隔物，图案化叠层绝缘体堆叠，去除牺牲侧壁间隔物，在图案化的层压绝缘体堆叠中形成通孔，以及将金属衬垫和导电材料沉积到通孔和槽中，其中层压绝缘体堆叠包括介电层 还包含氧化物和聚亚芳基。 沉积步骤防止层压的绝缘体叠层溅射到通孔中。 此外，沉积步骤包括清洁通孔和槽，可选地执行反应离子蚀刻或氩溅射清洗，在通孔和槽上沉积多个金属层，以及在通孔和槽中沉积铜。